Commit graph

21440 commits

Author SHA1 Message Date
Tom Rini
6eecaf5d0f Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net into next
- Fix some non-NULL terminated strings in the networking subsystem
- net: tsec: Mark tsec_get_interface as __maybe_unused
2021-09-29 07:58:20 -04:00
Robert Marko
65513f3c18 arm: dts: armada8040: Fix CP0 eMMC/SDIO support
During the migration to a single DTSI for the CP110-s specific pinctrl
compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics.
Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting
the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect
the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.

So, the mvebu-pinctrl driver check specifically for the
"marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.

Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl"
for CP0 and "marvell,8k-cps-pinctrl" for the CP1.
This is obviously incorrect as the pinctrl driver does not know about these.

So fix the regression by applying correct compatibles to the DTSI.
Regression found and tested on the Puzzle M801 board.

Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-29 07:13:27 +02:00
Rasmus Villemoes
24ea366add imx: imx7d-sdb: fix ethernet, sync .dts with linux
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0
(aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync
device tree with v5.5-rc1", but in the linux tree, these gpios have
always been GPIO_ACTIVE_HIGH ever since this node was introduced
around v4.13 (linux commit 184f39b5).

I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work
around the behaviour of the soft-spi driver back then, which
effectively defaulted to spi-mode 3 and not 0. That was arguably a bug
in the soft-spi driver, which then got fixed in 0e146993bb (spi: add
support for all spi modes with soft spi), but that commit then broke
ethernet on this board.

Fix it by setting the gpios as active high, which as a bonus actually
brings us in sync with the .dts in the linux source tree.

Without this, one gets

    Net:   Could not get PHY for FEC0: addr 0
    No ethernet found.

With this, ethernet (at least ping and tftp) works as expected from
the U-Boot shell.

Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joris Offouga <offougajoris@gmail.com>
Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-09-28 12:03:21 -04:00
Vladimir Oltean
19ef59f1e0 arch: powerpc: mpc85xx: free MDIO bus if mdio_register fails
If mdio_register fails, it is nice to not leave behind dangling
allocated memory.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:57 +03:00
Vladimir Oltean
fca315a382 arch: powerpc: mpc85xx: ensure mdiodev->name is NULL terminated after MDIO_NAME_LEN truncation
strncpy() simply bails out when copying a source string whose size
exceeds the destination string size, potentially leaving the destination
string unterminated.

One possible way to address is to pass MDIO_NAME_LEN - 1 and a
previously zero-initialized destination string, but this is more
difficult to maintain.

The chosen alternative is to use strlcpy(), which properly limits the
copy len in the (srclen >= size) case to "size - 1", and which is also
more efficient than the strncpy() byte-by-byte implementation by using
memcpy. The destination string returned by strlcpy() is always NULL
terminated.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Vladimir Oltean
7c2d5d1642 net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x"
After the discussion here:
https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/

which resulted in this patch:
https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/

and many other discussions before it, notably:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/

it became apparent that nobody really knows what "SGMII 2500" is.
Certainly, Freescale/NXP hardware engineers name this protocol
"SGMII 2500" in the reference manuals, but the PCS devices do not
support any "SGMII" specific features when operating at the speed of
2500 Mbps, no in-band autoneg and no speed change via symbol replication
. So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b
with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without
in-band autoneg and at a fixed speed" is indistinguishable from
"2500base-x without in-band autoneg", which is precisely what these NXP
devices support.

So it just appears that "SGMII 2500" is an unclear name with no clear
definition that stuck.

As such, in the Linux kernel, the drivers which use this SERDES protocol
use the 2500base-x phy-mode.

This patch converts U-Boot to use 2500base-x too, or at least, as much
as it can.

Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500
completely, but the mvpp2 driver seems to even distinguish between SGMII
2500 and 2500base-X. Namely, it enables in-band autoneg for one but not
the other, and forces flow control for one but not the other. This goes
back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500
is an MII protocol (connects a MAC to a PHY such as Aquantia), but the
two are practically indistinguishable through everything except use case.

NXP devices can support both use cases through an identical configuration,
for example RX flow control can be unconditionally enabled in order to
support rate adaptation performed by an Aquantia PHY. At least I can
find no indication in online documents published by Cisco which would
point towards "SGMII-2500" being an actual standard with an actual
definition, so I cannot say "yes, NXP devices support it".

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Vladimir Oltean
77b11f7604 net: replace the "xfi" phy-mode with "10gbase-r"
As part of the effort of making U-Boot work with the same device tree as
Linux, there is an issue with the "xfi" phy-mode. To be precise, in
Linux there was a discussion (for those who have time to read:
https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/)

which led to a patch:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881

TL;DR: "xfi" was standardized in Linux as "10gbase-r".

This patch changes the relevant occurrences in U-Boot to use "10gbase-r"
instead of "xfi" wherever applicable.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Vladimir Oltean
66fd01fe59 net: update NXP copyright text
NXP Legal insists that the following are not fine:

- Saying "NXP Semiconductors" instead of "NXP", since the company's
  registered name is "NXP"

- Putting a "(c)" sign in the copyright string

- Putting a comma in the copyright string

The only accepted copyright string format is "Copyright <year-range> NXP".

This patch changes the copyright headers in the networking files that
were sent by me, or derived from code sent by me.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Marek Vasut
4a60d3571b arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-28 18:50:55 +03:00
Marek Vasut
4527568e3f arm: socfpga: vining: Un-disable WDT in DT
The WDT on this system should be enabled, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-28 18:50:55 +03:00
Andy Shevchenko
5501fadb45 x86: tangier: acpi: Add GPIO card detection to SDHCI #2
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.

Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-28 18:50:55 +03:00
Andy Shevchenko
2f025b96bc x86: edison: Mark eMMC non-removable
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-28 18:50:54 +03:00
Tom Rini
4b62ba8fa2 ti: keystone: Migrate CONFIG_SOC_K2* to Kconfig
Move the individual keystone 2 SoC symbols to the mach Kconfig file,
select them as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27 21:38:34 -04:00
Tom Rini
f899cc1432 ti: keystone: Move away from CONFIG_SOC_KEYSTONE
We have individual SOC symbols for each keystone 2 platform.  Use the
existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to
encompass all of the keystone families.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27 21:38:34 -04:00
Tom Rini
1d1f98c8ee Various of-platdata improvements, including CONFIG_OF_REAL
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Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm into next

Various of-platdata improvements, including CONFIG_OF_REAL
2021-09-27 11:09:23 -04:00
Tom Rini
e908d20fcb Prepare v2021.10-rc5
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Merge tag 'v2021.10-rc5' into next

Prepare v2021.10-rc5
2021-09-27 09:45:36 -04:00
Heinrich Schuchardt
8ae8da10b3 sandbox: correct cpu nodes
The cpu nodes in arch/sandbox/dts/test.dts should conform to the devicetree
specification:

* property device_type must be set to "cpu"
* the reg property must be provided
* the cpu nodes must have an address

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
48609d0789 dm: gpio: Add of-platdata support
Add support for accessing GPIOs using of-plata. This uses the same
mechanism as for clocks, but allows use of the xlate() method so that
the driver can interpret the parameters.

Update the condition for GPIO_HOG so that it is not built into SPL,
since it needs SPL_OF_REAL which is not enabled in sandbox_spl.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
3e57ad907c irq: Tidy up of-platdata irq support
This function is available but not exported. More generally it does not
really work as intended.

Reimplement it and add a sandbox test too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
dcfc42b12f treewide: Try to avoid the preprocessor with OF_REAL
Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
9539738509 treewide: Use OF_REAL instead of !OF_PLATDATA
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
414cc15144 treewide: Simply conditions with the new OF_REAL
Use this new Kconfig to simplify the compilation conditions where
appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
7de8bd03c3 treewide: fdt: Move fdt_get_config_... to ofnode_conf_read...
The current API is outdated as it requires a devicetree pointer.

Move these functions to use the ofnode API and update this globally. Add
some tests while we are here.

Correct the call in exynos_dsim_config_parse_dt() which is obviously
wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Kristian Amlie
15e30106ce ARM: vexpress_ca9x4: Reintroduce board in order to use with QEMU.
vexpress_ca9x4 is seemingly the only board except for qemu_arm which
is able to run U-Boot correctly, using the `-M vexpress-a9` option to
QEMU. Building for qemu_arm and running qemu-system-arm with the `-M
virt` argument has a number of downsides, most importantly that it
only supports virtio storage drivers. This significantly reduces its
usefulness in testing memory card and Flash solutions, especially when
the tested images are from a third party source.

So therefore we reintroduce the vexpress_ca9x4 board in this commit,
with the explicit goal of using it with QEMU.

A number of differences to note from the original:

* Since the board was apparently unmaintained, I have now set myself
  as the maintainer.

* The board has been converted to use the driver model, which was the
  reason it was removed in the first place.

* The vexpress_ca15_tc2 and vexpress_ca5x2 boards, which were removed
  in the same commit, are not necessary for the QEMU use case, and
  have been omitted.

* An `mmc0` alias was introduced in the dts file. The mmc is not
  detected correctly without this, now that it's based on the device
  tree instead of the board's init function.

* A couple of other nodes were removed because they were problematic
  when trying to run the UEFI bootmgr. Once again, the primary use
  case here is QEMU, and these nodes are not needed for that to work.

* Unnecessary board init code has been removed, thanks to driver model
  and device tree.

* `CONFIG_OF_EMBED` has been enabled. I know this goes against
  recommended practice, but there doesn't seem to be any other way to
  pass the dtb to U-Boot in the QEMU scenario. Using the -dtb argument
  does not work, I suppose because U-Boot doesn't use the same
  mechanics as the kernel when it's booting.

* Load addresses have been changed to fit QEMU use case.

People wanting to get a more detailed, yet somewhat isolated, diff
between this and the original, can run this command:

  git diff c6c26a05b89f25a06e7562f8c2071b60fd0c9eac~1 -- \
      $( git diff-tree --diff-filter=A -r --name-only HEAD~1 HEAD)

(Make sure to either check out this commit first, or replace HEAD with
the commit ID of this commit)

Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
2021-09-24 14:30:46 -04:00
Patrick Delaunay
6493fa4c3d arm: use CONFIG_SUPPORT_PASSING_ATAGS
Simplify the bootm and the spl code by using the new config
CONFIG_SUPPORT_PASSING_ATAGS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-24 14:30:46 -04:00
Stefan Roese
4e062fc955 arm64: Kconfig: Enable usage of optimized memset/memcpy/memmove
This patch enables the use of the optimized memset(), memmove() &
memcpy() versions recently added on ARM64.

Please note that these optimized functions are now only enabled for
recent GCC versions (>= 9.4), as earlier GCC versions throw these
errors:

aarch64-linux-ar: warning: arch/arm/lib/memset-arm64.o: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0000000
...

Signed-off-by: Stefan Roese <sr@denx.de>
[trini: Make this default to off as it causes problems on some platforms still]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-24 07:49:16 -04:00
Stefan Roese
1e43bb6732 arm64: memset-arm64: Use simple memset when cache is disabled
The optimized memset uses the dc opcode, which causes problems when the
cache is disabled. This patch adds a check if the cache is disabled and
uses a very simple memset implementation in this case. Otherwise the
optimized version is used.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-09-24 07:48:06 -04:00
Stefan Roese
dbf6b14e0a arm64: arch/arm/lib: Add optimized memset/memcpy/memmove functions
Ported from https://github.com/ARM-software/optimized-routines

These files are included from this repository, including the latest
git commit ID:
string/aarch64/memcpy.S: afd6244a1f8d
string/aarch64/memset.S: e823e3abf5f8
string/asmdefs.h: e823e3abf5f8

Note that memmove is also handled by the memcpy function.

Please note that when adding these optimized functions as default memset
memcpy functions in U-Boot, U-Boot fails to boot on the LX2160ARDB.
After the initial ATF output, no U-Boot output is shown on the serial
console. Some exception is triggered here in the very early boot process
as some of the assembler opcodes need the caches to be enabled.

Because of this, a follow-up patch will add a check to use a simple
non-optimized memset for the "cache disabled" case.

Note:
I also integrated and tested with the Linux versions of these optimized
functions. They are similar to the ones now integrated but these ARM
versions are still a small bit faster.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-09-24 07:48:06 -04:00
Guillaume La Roque
df3ab898f6 arm: mediatek: merge board Kconfigs into mach-mediatek
On MediaTek boards we cannot override the SYS_BOARD / SYS_CONFIG_NAME
variables from defconfig.
This is because in board/mediatek/mtXXXX/Kconfig this value was override
by default due to the if CONFIG_TARGET_MTXXXX condition.

Merge all the Kconfigs to the mach-medatek/Kconfig.

This way:
- we only define SYS_{SOC,VENDOR} once
- all board definitions are in a single place, simplifying the build logic.

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
a69753f31d lmb: x86: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
7996b7e9f5 lmb: xtensa: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
1e0e557774 lmb: sh: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
This architecture also needs to cover U-Boot with LMB before booting
Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
eeaa3fe652 lmb: riscv: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Leo <ycliang@andestech.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
6a0890a61e lmb: nds32: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
a02c18f31f lmb: nios2: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
c16de86ec0 lmb: Remove imx board_lmb_reserve()
This function is clearly architecture specific code, not board specific
code. The only difference from the previous arm arch_lmb_reserve() is the
extra reservation of 16k of memory below the stack bottom, rather than
the 4k. The common code now also uses 16k alignment. Remove this custom
implementation, as it now behaves exactly as the common code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ye Li <ye.li@nxp.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
b1d0487cfe lmb: arm: Increase LMB alignment to 16k in arch_lmb_reserve_generic()
According to input NXP, the 4k alignment is not always sufficient.
Currently iMX works around this problem by implementing board specific
LMB reservation, however it is likely this could also occur on other
systems. Increase the LMB reservation alignment to 16k by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
1f391c3454 lmb: Switch to generic arch_lmb_reserve_generic()
Switch arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() to
arch_lmb_reserve_generic().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
2021-09-23 14:15:32 -04:00
Marek Vasut
cfa1971977 lmb: Always compile arch_lmb_reserve() into U-Boot on arc
The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
if CMD_BOOTM is not enabled. However, the arc variant of arch_lmb_reserve()
is only compiled in if CMD_BOOTM is enabled.

This currently does not trigger build error, because there is an empty
weak implementation of arch_lmb_reserve(), however that is not the
function that should be used on arc.

Fix this by moving the arch_lmb_reserve() implementation into common
code and always compile it in.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
8120e0681c lmb: Always compile arch_lmb_reserve() into U-Boot on arm
The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
if CMD_BOOT{I,M,Z} is not enabled. However, the arm32/arm64 variant of
arch_lmb_reserve() is only compiled in if CMD_BOOT{I,M,Z} is enabled.

This currently does not trigger build error, because there is an empty
weak implementation of arch_lmb_reserve(), however that is not the
function that should be used on arm32/arm64.

Fix this by moving the arch_lmb_reserve() implementation into common
code and always compile it in.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
270f8710f9 crc32: Add crc32 implementation using __builtin_aarch64_crc32b
ARMv8.0 has optional crc32 instruction for crc32 calculation. The
instruction is mandatory since ARMv8.1. The crc32 calculation is
faster using the dedicated instruction, e.g. 1.4 GHz iMX8MN gives:

  => time crc32 0x50000000 0x2000000
  time: 0.126 seconds # crc32 instruction
  time: 0.213 seconds # software crc32

Add implementation using the compiler builtin wrapper for the crc32
instruction and enable it by default, since we don't support any
platforms which do not implement this instruction.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
[trini: Make crc32_table guarded by CONFIG_ARM64_CRC32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Pierre-Clément Tosi
37479e65a3 armv8/cache.S: Triple with single instruction
Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.

Fix the comment as the tripled cache level is placed in x12, not x0.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-09-23 08:55:06 -04:00
Pierre-Clément Tosi
f050bfacc5 armv8/cache.S: Read sysreg fields through ubfx
Improve the file's readability and conciseness by using the appropriate
Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the
code easier to follow as it directly manipulates the offsets and widths
of the fields read from system registers, as they are expressed in the
Standard (ARM ARM). This has the added benefit (albeit arguably
negligible) of reducing the final code size.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-09-23 08:55:06 -04:00
Tom Rini
7b57e56739 First set of u-boot-at91 features for the 2022.01 cycle
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Merge tag 'u-boot-at91-2022.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.01 cycle:

This feature set includes : the support for CPU driver for arm926
(sam9x60 device); changes required for OP-TEE boot for sama5d2_xplained
and sama5d27_som1_ek boards; QSPI boot configuration for sama5d2_icp;
starting to remove old Kconfig unused symbols from config_whitelist.txt
(work will take more time); also small fixes and updates in mach, DT,
configs, etc.
2021-09-22 21:17:39 -04:00
Marek Vasut
c3880e6597 arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Marek Vasut
e21bbffa1d arm: socfpga: vining: Un-disable WDT in DT
The WDT on this system should be enabled, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Andy Shevchenko
57e2c0a86f x86: tangier: acpi: Add GPIO card detection to SDHCI #2
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.

Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-22 21:50:35 +08:00
Andy Shevchenko
e45066f48f x86: edison: Mark eMMC non-removable
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-22 21:50:35 +08:00
Patrick Delaunay
cf39d0c29d arm: dts: stm32mp1: use ssbl partition name for U-Boot
Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.

The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.

Fixes: b73e8bf453 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-21 09:22:01 +02:00
Eugen Hristev
d65b84a1d0 ARM: dts: at91: update flexcom defines using include file
Replace the number in the flexcom-mode property with the define from the
include file.
This corresponds to the approach in Linux kernel.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21 10:08:24 +03:00