Commit graph

536 commits

Author SHA1 Message Date
Tom Rini
3431b392ad Patch queue for efi - 2016-10-19
Highlights this time around:
 
   - Add run time service (power control) support for PSCI (fixed in v3)
   - Add efi gop pointer exposure
   - SMBIOS support for EFI (on ARM)
   - efi pool memory unmap support (needed for 4.8)
   - initial x86 efi payload support (fixed up in v2)
   - various bug fixes
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2016-10-19

Highlights this time around:

  - Add run time service (power control) support for PSCI (fixed in v3)
  - Add efi gop pointer exposure
  - SMBIOS support for EFI (on ARM)
  - efi pool memory unmap support (needed for 4.8)
  - initial x86 efi payload support (fixed up in v2)
  - various bug fixes

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/tables_csum.h
2016-10-19 07:48:16 -04:00
Simon Glass
65e4c0b168 x86: efi: Add EFI loader support for x86
Add the required pieces to support the EFI loader on x86.

Since U-Boot only builds for 32-bit on x86, only a 32-bit EFI application
is supported. If a 64-bit kernel must be booted, U-Boot supports this
directly using FIT (see doc/uImage.FIT/kernel.its). U-Boot can act as a
payload for both 32-bit and 64-bit EFI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-10-19 09:01:53 +02:00
Alexander Graf
94eaa79cec cpu: Add get_vendor callback
The CPU udevice already has a few callbacks to retreive information
about the currently running CPUs. This patch adds a new get_vendor()
call that returns the vendor of the main CPUs.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-19 09:01:51 +02:00
Alexander Graf
6f192ddcbd cpu: Add DMTF id and family fields
For SMBIOS tables we need to know the CPU family as well as CPU IDs. This
patches allocates some space for them in the cpu device and populates it
on x86.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-19 09:01:51 +02:00
Simon Glass
f822403f01 x86: Add implementations of setjmp() and longjmp()
Bring in these functions from Linux v4.4. They will be needed for EFI loader
support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-18 15:58:50 +08:00
Simon Glass
b02e4044ff libfdt: Bring in upstream stringlist functions
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.

This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :

   604e61e fdt: Add functions to retrieve strings
   8702bd1 fdt: Add a function to get the index of a string
   2218387 fdt: Add a function to count strings

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-13 13:54:10 -06:00
Bin Meng
2d3c573ee6 x86: coreboot: Convert to use DM coreboot video driver
This converts coreboot to use DM framebuffer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-12 10:58:24 +08:00
Simon Glass
2545fa59f8 x86: ivybridge: Tidy up enable_clock_gating() for 64-bit
Fix the hex case and remove unused brackets. Use ~0U instead of ~0UL to
allow compilation on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
4e0318c32f x86: ivybridge: Fix PCH power setup
At present pch_power_options() has the arguments to writel() around the
wrong way. Fix this and update it to compile on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
21b3b66ace x86: Correct address casts in interrupt code
We should cast an address to unsigned long, not u32.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
d30b3103a5 x86: Correct address casts in cpu code
We should cast an address to unsigned long, not u32.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
35233da98a x86: Allow interrupts to be disabled in 64-bit mode
Update the code to support both 32-bit and 64-bit modes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
b6409ec302 dm: x86: Move link to use driver model for video
Update the configuration to use the new driver. Drop the existing plumbing
code and unused header files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
443ffe509c dm: x86: Move samus to use new driver model support
Update the samus driver to avoid the direct call to the video BIOS setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Stefan Roese
5572367cc5 x86: baytrail: Add 2nd eMMC controller to the PCI probe list
With this addition, the eMMC device available on the congatec and DFI
BayTrail SoM is detected correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Masahiro Yamada
0a8547a250 x86: squash lines for immediate return
arch_cpu_init() can be simpler by this refactoring.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-23 17:53:49 -04:00
Simon Glass
4cc00f0611 x86: Add debugging when cpu_common_init() fails
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30 09:26:05 +08:00
Simon Glass
e6294e0579 x86: ivybridge: Allow microcode to be collated
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.

Adjust the ivybridge code to avoid assuming this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30 09:26:05 +08:00
Simon Glass
fda4fa8195 x86: Add debugging when a microcode update fails
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30 09:26:05 +08:00
Stefan Roese
d7b935bf62 x86: baytrail: Add SIO HS-UART clock setup
To support the BayTrail internal SIO HS UART, the internal UART clock
needs to get configured. This patch adds support for this clock
configuration which will be done, if the PCI device(s) are found.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-16 11:44:09 +08:00
Tom Rini
b8e599746c Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-07-12 08:15:17 -04:00
Simon Glass
9532fe3b40 x86: link: Correct a failure in DRAM init
With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.

Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-07-12 13:59:45 +08:00
Bin Meng
cf7108b320 x86: quark: Introduce ACPI global NVS
This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
2047390abc x86: baytrail: Introduce ACPI global NVS
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
377656b2cc x86: baytrail: Introduce a Kconfig option for the internal UART
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.

So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Simon Glass
6cd2602d61 x86: fdt: Drop the unused compatible strings in fdtdec
We have drivers for several more devices now, so drop the strings which are
no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-07-11 14:06:44 -06:00
Bin Meng
ff6e156966 x86: coreboot: Remove the dummy pch driver
There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-29 10:08:15 +08:00
Bin Meng
d8906c1f3f x86: Probe pinctrl driver in cpu_init_r()
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

 - Pin's PADs only gets configured when GPIO driver is probed, which
   is not done by default. This leaves the board in a partially
   functional state as we must initialize PADs correctly to get
   perepherals fully working.
 - The probe routine of pinctrl driver is called multiple times, as
   normally there are multiple GPIO controllers. It should really
   be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
2016-06-12 12:19:35 +08:00
Bin Meng
d3d664725b x86: baytrail: acpi: Fix I/O APIC ID in the MADT table
So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
7ee371063f x86: quark: Generate ACPI FADT/MADT tables
Generate quark platform-specific FADT/MADT tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
b813ea9a14 x86: broadwell: Correct I/O APIC ID
Currently ID 2 is assgined to broadwell I/O APIC, however per
chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change
I/O APIC ID to 4 to avoid conflict.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:42 +08:00
Bin Meng
911d6f6932 x86: quark: Assign a unique I/O APIC ID
After power-on, both LAPIC and I/O APIC appear with the same APIC ID
zero, which creates an ID conflict. When generating MP table, U-Boot
reports zero as the LAPIC ID in the processor entry, and zero as the
I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment
entries. Such MP table confuses Linux kernel and finally a kernel
panic is seen during boot:

  BUG: unable to handle kernel paging request at ffff9000
  IP: [<c101d462>] native_io_apic_write+0x22/0x30
  *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000
  Oops: 0002 [#1]
  Modules linked in:
  Pid: 1, comm: swapper Tainted: G        W    3.8.7 #3 intel galileo/galileo
  EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0
  EIP is at native_io_apic_write+0x22/0x30
  ...
  Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:42 +08:00
Bin Meng
e2126711af x86: Call lapic_setup() in interrupt_init()
Let's configure LAPIC in a common place - interrupt_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
aaaa55751a x86: Remove SMP limitation in lapic_setup()
At present LAPIC is enabled and configured as virtual wire mode
in lapic_setup() only when CONFIG_SMP is on. This limitation is
however not necessary as for uniprocessor this is still needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
3299be2479 x86: Don't touch IA32_APIC_BASE MSR on Intel Quark
Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
d19c90747d x86: Reserve configuration tables in high memory
When SeaBIOS is on, reserve configuration tables in reserve_arch().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
0c2b7eef97 x86: Unify reserve_arch() for all x86 boards
Instead of asking each platform to provide reserve_arch(),
supply it in arch/x86/cpu/cpu.c in a unified way.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
10d569ea1a x86: Fix up PIRQ routing table checksum earlier
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksum field not being zero before fix up, since
the checksum has already been calculated in the first run.

To fix this, move the checksum fixup to create_pirq_routing_table(),
so that copy_pirq_routing_table() only does what its function name
suggests: copy the table to somewhere else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
1e2f7b9e8e x86: Call board_final_cleanup() in last_stage_init()
At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, VxWorks or Windows.

Move the call to last_stage_init() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Miao Yan
494ec0d093 x86: qemu: rename qemu/acpi_table.c
Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved
to qfw core, this file only contains code for installing e820 table.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
eece493a7a cmd: qfw: bring ACPI generation code into qfw core
Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
1868659002 cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]
Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
331ba7db6c x86: qemu: add comment about qfw register endianness
This patch adds some comments about qfw register endianness for clarity.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
2e82e745a4 x86: qemu: move x86 specific operations out of qfw core
The original implementation of qfw includes several x86 specific
operations, like directly calling outb/inb and using some inline
assembly code which prevents it being ported to other architectures.

This patch adds callback functions and moves those to arch/x86/

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
fcf5c04193 x86: qemu: split qfw command interface and qfw core
This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.

Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
05dd6f183c cmd: qfw: remove qemu_fwcfg_free_files()
This patch is part of the qfw refactor work.

The qemu_fwcfg_free_files() function is only used in error handling in
ACPI table generation, let's not make this a core function and move it
to the right place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
34865a65c4 x86: qemu: fix ACPI Kconfig options
CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI table from QEMU's fw_cfg interface.

But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop
our own ACPI implementation", there is only one way to support ACPI table
for QEMU targets which is the fw_cfg interface. Having two Kconfig options
for this purpose is not necessary any more, so this patch consolidates
the two.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Tom Rini
dd6f3abbb8 x86: qemu: Move qfw command over to cmd and add Kconfig entry
- Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into
  cmd/qemu_fw_cfg.c
- Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h
- Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Bin Meng
4470f2d51c x86: baytrail: Generate ACPI FADT/MADT tables
FADT/MADT tables are platform specific. Generate them for BayTrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
d4e61f505b x86: irq: Enable SCI on IRQ9
By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2016-05-23 15:18:00 +08:00