Grzegorz Bernacki
334e442e6f
Set ips dividor to 1/4 of csb clock.
...
Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2008-01-17 09:31:58 +01:00
John Rigby
51b67d06fa
ADS5121: MAX slew rate for PATA pins
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Signed-off-by: John Rigby <jrigby@freescale.com>
2008-01-13 23:36:22 +01:00
Wolfgang Denk
b1b54e3520
Coding style cleanup, update CHANGELOG
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Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-08-02 21:27:46 +02:00
Rafal Jaworowski
8993e54b6f
[ADS5121] Support for the ADS5121 board
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The following MPC5121e subsystems are supported:
- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
2007-07-27 14:43:59 +02:00
