5 commits

Author	SHA1	Message	Date
Simon Glass	0621b5e1ee	cbfs: Don't require the CBFS size with cbfs_init_mem() ... The size is not actually used since it is present in the header. Drop this parameter. Also tidy up error handling while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2020-05-27 14:40:09 +08:00
Simon Glass	f7ae49fc4f	common: Drop log.h from common header ... Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>	2020-05-18 21:19:18 -04:00
Simon Glass	52f2423804	common: Drop bootstage.h from common header ... Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>	2020-05-18 17:33:33 -04:00
Simon Glass	c793dbdb90	x86: fsp: Allow skipping init code when chain loading ... It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2020-04-30 17:40:16 +08:00
Simon Glass	cf87d3b503	x86: fsp: Add FSP2 base support ... Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>	2019-12-15 11:44:16 +08:00