Commit graph

19357 commits

Author SHA1 Message Date
Shaveta Leekha
c6cef92f63 powerpc/qixis: enable qixis dump command and add switch dumping command
Remove #ifdef so that "qixis dump" command is always available

Add "qixis_reset switch" command to dump switch settings
Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from
registers to figure out switch settings. Not all bits are available.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
York Sun
b5b06fb7b0 powerpc/b4860qds: Added Support for B4860QDS
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,  ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
  16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
  8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
  RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
  connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
  connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
  configuration reset source. The RCW source is set by appropriate
  DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
	- On-board eCWTAP controller with ETH and USB I/F
	- JTAG/COP 16-pin header for any external TAP controller
	- External JTAG source over AMC to support B2B configuration
	- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
	- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
  DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
  - total four refclk, including CPRI clock scheme

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
Prabhakar Kushwaha
db9a807054 powerpc/mpc85xx:Fix Core cluster configuration loop
Different personalities/derivatives of SoC may have reduced cluster. But it is
not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have
DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters".

EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC
which may not be valid for the personality.
So add initiator type check to find valid cluster.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Prabhakar Kushwaha
2ae4e8d958 board/freescale/common:Add support of QTAG register
QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE
fields. These fields have FPGA build version, image name and build date
information.

Add support to parse these fields to have complete FPGA image information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e1dbdd8152 powerpc/mpc85xx:Add support of B4420 SoC
B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900
and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and
reduced target frequencies.

Key differences between B4860 and B4420
----------------------------------------
B4420 has:
1. Fewer e6500 cores: 1 cluster with 2 e6500 cores
2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
3. Single DDRC
4. 2X 4 lane serdes
5. 3 SGMII interfaces
6. no sRIO
7. no 10G

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Poonam Aggrwal
e394ceb17f powerpc/mpc85xx: Few updates for B4860 cpu changes
- Added some more serdes1 and serdes2 combinations
  serdes1= 0x2c, 0x2d, 0x2e
  serdes2= 0x7a, 0x8d, 0x98
- Updated Number of DDR controllers to 2.
- Added FMAN file for B4860, drivers/net/fm/b4860.c

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Hongtao Jia
86a194b733 powerpc/mpc8544ds: Add USB controller support for MPC8544DS
USB controller in uboot is a required feature for MPC8544DS. Without this
support there is no 'usb' command in uboot.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Hongtao Jia
238e146791 powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs
The controller interleaving only takes the usable memory mapped to cs0. In
the case of bank interleaving not enabled, only half of dual-rank DIMM will
be used.

For single-rank DIMM bank interleaving will be auto disabled.

Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:09 -06:00
York Sun
9730b7bc11 powerpc/t4240qds: Update IFC timing for NOR flash
Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:09 -06:00
Prabhakar Kushwaha
9427ba5c27 boards/T4240qds:Fix IFC AMASK init as per FPGA register space
T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's
Address Mask Registers is initialised 64K size.

So Fix the Address Mask Register initilisation as 4K

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:09 -06:00
Prabhakar Kushwaha
ac13eb5de0 board/T4240qds:Fix TLB and LAW size of NAND flash
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.

So Update TLB and LAW size of NAND flash accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:09 -06:00
York Sun
2d9f26b693 powerpc/mpc85xx: Reserve default boot page
The boot page in memory is already reserved so OS won't overwrite.
As long as the boot page translation is active, the default boot page
also needs to be reserved in case the memory is 4GB or more.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Timur Tabi
de757a7af0 powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c
Static variables should be defined in C files, not header files, because
otherwise every C file that #includes the header file will generate a
duplicate of the variables.  Since the vsc3316_xxx[] arrays are only
used by t4qds.c anyway, just put the variables there.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Shaohui Xie
220d506af3 powerpc/p2041: move Lanes mux to board early init
Lanes mux currently is configured in eth.c when initializing FMAN ethernet
ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to
p2041rdb.c which implements a board-specific initialization and will be
called at early stage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Tom Rini
88ba6d530d Merge branch 'master' of git://git.denx.de/u-boot-i2c 2013-01-29 15:36:27 -05:00
Tom Rini
06b02c58d2 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2013-01-29 15:36:23 -05:00
Michael Jones
019be4af64 Remove unused CONFIG_SYS_I2C_BUS[_SELECT]
"CONFIG_SYS_I2C_BUS" and "CONFIG_SYS_I2C_BUS_SELECT" don't appear anywhere
outside of config files.

Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-01-29 06:40:01 +01:00
Marek Vasut
49c28b564b i2c: mxs: Staticize the functions in the driver
The local functions in the mxs i2c driver are not marked static, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2013-01-29 06:39:52 +01:00
Otavio Salvador
81ca840976 mx23evk: Add initial board support
The following features are supported:
 * 128 MB DDR1 SDRAM
 * DUART
 * SD/MMC Card Socket

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-28 11:51:04 +01:00
Otavio Salvador
38fc15d86c mx23_olinuxino: Add default environment
This adds a default environment with support for MMC booting.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-01-28 11:50:11 +01:00
Marek Vasut
13b1ebdec6 mxs: mmc: mx23_olinuxino: Add MMC support
Add support for the MMC attached to SSP1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
e5b380ac68 mxs: mmc: Fix the MMC driver for MX23
The MX23 has different layout of DMA channels. Fix the MMC
driver to support MX23.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
90bc2bf297 mxs: mmc: Allow overriding default card detect implementation
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Otavio Salvador
8000d8a826 mxs: mmc: Fix MMC reset on iMX23
This does the same reset mask as done in v3.7 Linux kernel code.
The block is properly configured for MMC operation that way.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
f3801e2b9b mxs: ssp: Add SSP registers map for MX23
The MX23 SSP register layout differs from MX28 in certain bits,
adjust the register layout accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Marek Vasut
0e5c05efb4 mxs: dma: Fix APBH DMA driver for MX23
The MX23 has less channels for the APBH DMA, sligtly different register
layout and some bits in those registers are placed differently. Reflect
this in the driver. This patch fixes MMC/DMA issue on MX23.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:00 +01:00
Troy Kisky
3236921968 mx6qsabrelite: search mii phy address 4-7
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:51 +01:00
Troy Kisky
fe428b909b net: fec_mxc: get phydev before fec_probe
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:51 +01:00
Troy Kisky
4dc27eed52 net: fec_mxc: only call phy_connect in fec_probe
This allows us to create the phydev before calling
fec_probe in later patch.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
ef8e3a3bbf net: fec_mxc: use fec_set_dev_name to set name
This allows us to create the phydev before calling
fec_probe in later patch.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
1adb406b01 phy: add phy_find_by_mask/phy_connect_dev
It is useful to be able to try a range of
possible phy addresses to connect.

Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
eef2448039 net: fec_mxc: have fecmxc_initialize call fecmxc_initialize_multi
Having only one call to fec_probe will ease the changing of its
parameters.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
575c5cc06f net: fec_mxc: change fec_mii_setspeed parameter
Only the hardware ethernet registers are needed
for this function, so don't pass the more general
structure. I'm trying to separate MII and fec.

This also fixes MX28 fec_mii_setspeed use on secondary ethernet port

This was found by inspection of the code and should be
checked on real hardware.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
09439c3197 net: fec_mxc: delete CONFIG_FEC_MXC_MULTI
It is more logical to test for CONFIG_FEC_MXC_PHYADDR
to determine whether to define the function fecmxc_initialize.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:50 +01:00
Troy Kisky
c30eab2ddd doc/README.fec_mxc: add documentation
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:49 +01:00
Fabio Estevam
f093088214 mxs: Use __weak annotation to simplify code
Using the __weak annotation can make the code cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-01-28 06:54:19 +01:00
Fabio Estevam
6e08385715 tools: imximage: Let .name field be more generic
Since this structure is not i.MX5x specific, remove the '5x' to make it more
generic.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-28 06:49:51 +01:00
Fabio Estevam
e4f8d96423 mx6qsabre_common: Let mmc partition be board specific
commit 49ea0ff5 (49ea0ff5) introduced CONFIG_SYS_MMC_ENV_PART into mx6qsabresd.h
to store the mmc partition, but in order for it to have effect we should place
it into 'mmcpart' variable.

Also add CONFIG_SYS_MMC_ENV_PART into mx6qsabreauto.h.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-28 06:45:18 +01:00
Knut Wohlrab
73448b1f80 mx6qsabreauto: enable USB host interface
The USB host interface is routed to plug USB1/J30 on the mother board.

Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com>
2013-01-28 06:43:58 +01:00
Marek Vasut
8303ed128a mxs: Boost the memory power supply
The memory power supply on MX23 didn't pump out enough juice into
the DRAM chip, thus caused occasional memory corruption. Fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-01-28 06:40:38 +01:00
Gabor Juhos
67d80c9f97 MIPS: start.S: don't save flush_cache parameters in advance
Saving the parameters in advance unnecessarily complicates
the code. The destination address is already saved in the
's2' register, and that register is not clobbered by the
copy loop. The size of the copied data can be computed
after the copy loop is done.

Change the code to compute the size parameter right
before calling flush_cache, and set the destination
address parameter in the delay slot of the actuall
call.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:40:15 +01:00
Gabor Juhos
248fe03f53 MIPS: start.S: simplify relocation offset calculation
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.

The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.

This approach makes the code a bit simpler because
it needs two instructions only.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:40:07 +01:00
Gabor Juhos
b2fe86f887 MIPS: start.S: save reused arguments earlier in relocate_code
Save the reused parameters at the beginning
of the 'relocate_code' function. This makes
the function a bit more readable.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:59 +01:00
Gabor Juhos
f321b0f99f MIPS: start.S: set sp register directly
The current code uses two instructions to load
the stack pointer into the 'sp' register.

This results in the following assembly code:

    468:   3c088040        lui     t0,0x8040
    46c:   251d0000        addiu   sp,t0,0

The first instuction loads the stack pointer into
the 't0' register then the value of the 'sp' register
is computed by adding zero to the value of the 't0'
register. The same issue present on the 64-bit version
as well:

    56c:   3c0c8040        lui     t0,0x8040
    570:   659d0000        daddiu  sp,t0,0

Change the code to load the stack pointer directly
into the 'sp' register. The generated code is functionally
equivalent to the previous version but it is simpler.

  32-bit:
    468:   3c1d8040        lui     sp,0x8040

  64-bit:
    56c:   3c1d8040        lui     sp,0x8040

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:51 +01:00
Gabor Juhos
5b7dd8163d MIPS: start.S: fix boundary check in relocate_code
The loop code copies more data with one than
necessary due to the 'ble' instuction. Use the
'blt' instruction instead to fix that.

Due to the lack of suitable hardware the Xburst
specific code is compile tested only. However the
change is quite obvious.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-27 16:39:43 +01:00
Gabor Juhos
14fdd1a8bf MIPS: start{, 64}.S: fill branch delay slots with NOP instructions
The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 21:09:34 +01:00
Gabor Juhos
0ef48d4c89 MIPS: convert IO port accessor functions to 'static inline'
The currently used 'extern inline' directive causes
the following compiler warnings if CONFIG_SWAP_IO_SPACE
is defined:

  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outlc' which is not static [enabled by default]
  <...>/include/asm/io.h:345:1: warning: '__fswab32' is static but used in inline function '__outl' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outwc' which is not static [enabled by default]
  <...>/include/asm/io.h:344:1: warning: '__fswab16' is static but used in inline function '__outw' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl_p' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inlc' which is not static [enabled by default]
  <...>/include/asm/io.h:341:1: warning: '__fswab32' is static but used in inline function '__inl' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw_p' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inwc' which is not static [enabled by default]
  <...>/include/asm/io.h:340:1: warning: '__fswab16' is static but used in inline function '__inw' which is not static [enabled by default]

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 21:07:19 +01:00
Gabor Juhos
be002d0070 MIPS: use inline directive for __in*s functions
All other IO accessor functions are using the
'inline' directive. Use that also for the __in*s
to make it consistent with the other variants.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-22 20:52:08 +01:00
Troy Kisky
71a988aa63 imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.

The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile

.gitignore was updated to ignore .cfgtmp files.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-22 10:20:13 +01:00
Otavio Salvador
0023997709 mxs: Add MX23 quirks into the clock code
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:22 +01:00