Commit graph

2 commits

Author SHA1 Message Date
Peng Fan
ad7af5d7e4 imx6: cache: disable L2 before touching Auxiliary Control Register
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"

So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2016-05-06 10:43:39 -04:00
Adrian Alonso
ab09e72866 arm: imx: common rework cache settings for imx6
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:53 +02:00