Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The HOST_MODE register must be set to 0 when the IP is operated in 16bit
mode, otherwise 16bit access to the data FIFO may fail.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable the HS200 on RCar Gen3 platforms, since the SDHI core supports it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Export the matsu_sd_{read,write}l() common register access
functions, so that they can be used by other drivers sharing
the common code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Factor out the regulator handling into set_ios and add support for
selecting pin configuration based on the voltage to support UHS modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Handle bus width 0 as 1-bit bus to assure valid content of
MATSU_SD_OPTION register WIDTH field.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop the ad-hoc DT caps parsing in favor of common framework function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Since the Renesas SDHI has it's own custom driver sharing the
common code with Uniphier one, adjust the Kconfig entries.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add Kconfig entry for the Renesas SDHI variant of the controller
and split the Makefile entries accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Factor out common code from the uniphier SD driver, change the prefix
of the functions from uniphier_sd_ to matsu_sd_ and create separate
renesas-sdhi.c driver. Thus far, all the code is still compiled when
CONFIG_UNIPHIER_MMC is selected and there is no functional change.
This patch is a preparation for further split of the SoC specific
parts of the Matsushita SD driver, used both on Uniphier and R-Car.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable the HUSH shell, since it is far more capable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add JTAG recovery support into the M2 Porter TPL. This allows the
TPL to be loaded over JTAG, initialize the system, wait for the
JTAG debugger to load U-Boot image into RAM and then resume and
start U-Boot from RAM.
The procedure is as follows:
1) Load u-boot-tpl.bin to 0xe6300000
2) Write magic number 0x1337c0de to 0xe6300020
TPL checks for this particular magic and starts JTAG recovery
if this number is present. This is not present by default.
3) Start U-Boot TPL from 0xe6300000
4) Wait for a message from TPL on UART indicating JTAG boot:
"JTAG boot detected!"
5) Halt the system in JTAG debugger
6) Load U-Boot image (u-boot.img) to 0x4fffffc0
7) Write magic number 0xb33fc0de to 0xe6300024
TPL checks for this particular magic to verify that the U-Boot
image was loaded into DRAM by the JTAG debugger.
8) Resume the system in JTAG debugger
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add and enable TPL on M2 Porter. The TPL must fit into 16 kiB due
to the Gen2 BootROM restriction. The TPL is running from MERAM and
is capable of performing the initial initialization of PFC, Clock,
GPIO, LBSC, DBSC and QSPI NOR. DBSC is responsible for bringing up
the DDR DRAM access. The TPL is capable of loading the next stage,
U-Boot, from either SPI NOR or UART as a fallback. If either does
provide a valid U-Boot uImage, the system stops, which allows the
operator to load U-Boot ie. via JTAG and start it manually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Skip the cache initialization, which can be done later on in U-Boot
proper, since this interferes with early DRAM initialization in TPL.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Pull the SPL code from porter.c into a separate file in
preparation for the addition of system initialization code.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add TPL config symbols for RAM loading matching the SPL ones.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
This patch is a preparation for adding TPL support for RAM loading.
CONFIG_IS_ENABLED allows for proper handling of the U-Boot/SPL/TPL
differences in config symbol names.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
The tiny variants of memset and memcpy implementations can be
built for TPL as well, check whether a TPL build is in progress
and avoid including the default variants.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
This patch fixes a situation where CONFIG_DM_SERIAL is enabled for
regular U-Boot and SPL, but not for TPL. In that case, the build
will try to include serial-uclass into the TPL nonetheless, because
CONFIG_DM_SERIAL is set.
The solution is to check if the build is for SPL or TPL and in that
case, check if CONFIG_$(SPL_TPL_)DM_SERIAL is also set. Only in that
case, include serial-uclass.c . If the build is for regular U-Boot,
CONFIG_BUILD is not set, so only check if CONFIG_DM_SERIAL is set
and if so, include serial-uclass.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Add Kconfig entry for CONFIG_TPL_YMODEM_SUPPORT symbol to match the SPL one.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Add Kconfig entry for CONFIG_TPL_SPI_LOAD symbol to match the SPL one.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Add Kconfig entry for CONFIG_SPL_SPI_LOAD symbol and move all
configurations using it to Kconfig.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs
and an USB3 PHY. This patch adds drivers for these for the standard generic
PHY interface and supports the power-on/off calls and set the Host mode by
default.
They are based on the excellent work from Martin Blumenstingl merged in linux.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
DWC3 Ips can have more than 1 PHY for USB2 and 1 PHY for USB3, add support
for a generic number of PHYs and adapt the code to handle a generic
number of PHYs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This is a port of the dwc3-of-simple driver from Linux to enable/deassert
clock and resets of a simple DWC3 Controller HW glue.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add an option to get the clock speed from the device tree, hence adding
compatibility with DM clock drivers.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Since bus translations are now fully supported, use a plain
"dev_read_addr" to get the device address from the device tree.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The fpgamap interface has been switched to a "single function + data
size" interface. Reflect this change in the IHS I2C driver.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The commit implement a gpio-based software deblocking. The code
extract I2C pins description from device tree, switch pins to GPIO
mode, toggle SCL until slave release SDA, send I2C stop and switch
I2C pins back to I2C mode.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
The commit describe usage of gpios and pinctrl device tree
properties in order to enable gpio-based software deblocking.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
The mutex lock and unlock functions are stubbed out and mutex_is_locked
was 0. This caused asserts to fail in ubifs code when checking that the
mutex was locked. For example,
UBIFS assert failed in ubifs_change_lp at 540
UBIFS assert failed in ubifs_release_lprops at 278
Assume that the "mutex" is locked since that is the normal case when it
is checked in the ubifs code.
Signed-off-by: Bradley Bolen <bradleybolen@gmail.com>
Update scripts/checkpatch.pl from upstream.
One of the many corrections is not creating an error for cover-letters.
Reintroduce U-Boot's
5c761ce586
checkpatch.pl: Add warning for new __packed additions
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Using sizeof gives the size of the pointer only, not the string. This
could easily lead to crashes when using -l argument.
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
The most significant change is the addition of the --self-test option
which allows to run a consistency check on all MAINTAINERS files.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This patch adds the bulk clock API tests for the sandbox test suite.
It's very similar to the main test but only uses the _bulk() API and
checks if the clocks are correctly enabled/disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a "bulk" API to the clock API in order to get/enable/disable
/release a group of clocks associated with a device.
This bulk API will avoid adding a copy of the same code to manage
a group of clocks in drivers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
