Commit graph

6 commits

Author SHA1 Message Date
Jagan Teki
4927e2e8d3 clk: sunxi: Add Allwinner A31 CLK driver
Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_gate table
  for A31, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
  for A31, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
c8e743c1e8 clk: sunxi: Add Allwinner A10s/A13 CLK driver
Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10s/A13, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
6590bd8c47 clk: sunxi: Add Allwinner A10/A20 CLK driver
Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10/A20, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
e945816efb clk: sunxi: Add Allwinner H3/H5 CLK driver
Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for
  H3/H5, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
  H3/H5, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
99ba430870 reset: Add Allwinner RESET driver
Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
0d47bc7056 clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30