Commit graph

45 commits

Author SHA1 Message Date
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Lokesh Vutla
8a8af8a2fd cmd: ti: Generalize cmd_ddr3 command
Keystone and DRA7 based TI platforms uses same
EMIF memory controller. cmd_ddr3 command is customized
for keystone platforms, make it generic so that it can
be re used for DRA7  platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:26 -05:00
Rex Chang
4849d95407 board: ti: K2G FC SoC 1GHz and DDR3 1066 MT/s support
Added support for K2G EVM with FlipChip SoC of which
ARM/DDR3 runs at 1GHz/1066 MT/s. The patch is also
backward compatible with old revision EVM and EVM
with WireBond SoC. Their ARM/DDR3 run at 600MHz/800 MT/s.

The new SoC supports 2 different speeds at 1GHz and 600MHz.
Modyfied the CPU Name to show which SoC is used in the EVM.
Modified the DDR3 configuration to reflect New SoC supports
2 different CPU and DDR3 speeds, 1GHz/1066MT and 600MHz/800MT.

Added new inline function board_it_k2g_g1() for the new FlipChip 1GHz,
and set the u-boot env variable board_name accordingly.

Modified findfdt script in u-boot environment variable to include new k2g board type.

Signed-off-by: Rex Chang <rchang@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-01-19 15:49:24 -05:00
Jean-Jacques Hiblot
f844d5f4e6 omap: Update the base address of the MMC controllers
Align the base address defined in header files with the base address used
in the DTS. This will facilitate the introduction of the DMA support.

Of all HSMMC users, only omap3 doesn't have the 0x100 reserved region at
the top. This region will be used to determine if the controller supports
DMA transfers

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-18 22:04:21 -05:00
Madan Srinivas
1d73ce6f68 arm: mach-keystone: Updates mon_install for K2G HS
On early K2 devices (eg. K2HK) the secure ROM code does not support
loading secure code to firewall protected memory, before decrypting,
authenticating and executing it.

To load the boot monitor on these devices, it is necessary to first
authenticate and run a copy loop from non-secure memory that copies
the boot monitor behind firewall protected memory, before decrypting
and executing it.

On K2G, the secure ROM does not allow secure code executing from
unprotected memory. Further, ROM first copies the signed and encrypted
image into firewall protected memory, then decrypts, authenticates
and executes it.

As a result of this, we cannot use the copy loop for K2G. The
mon_install has to be modified to pass the address the signed and
encrypted secure boot monitor image to the authentication API.

For backward compatibility with other K2 devices and K2G GP,
the mon_install API still supports a single argument. In this case
the second argument is set to 0 by u-boot and is ignored by ROM

Signed-off-by: Thanh Tran <thanh-tran@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-26 11:26:51 -04:00
Cooper Jr., Franklin
f8b4a2d7e2 ARM: keystone2: Add additional fields used for DDR3 configuration
Future boards will need to configure DDR3 registers in a slightly
different manner. Support this by defining additional variables and
defines that will be utilized later.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-07-10 14:25:56 -04:00
Lokesh Vutla
ee3c6532be ARM: keystone2: Add support for getting external clock dynamically
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 12:34:29 -04:00
Lokesh Vutla
c5f177debc ARM: k2g: Add support for dynamic programming of PLL based on SYSCLK
K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 12:34:29 -04:00
Masahiro Yamada
43ebbfc39f ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()
The KeyStone platform has its own clk_get_rate() but its prototype
is different from that of the common-clk (clk-uclass) framework.

Prefix the KeyStone specific implementation with ks_ in order to
avoid name-space conflict.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-08 09:33:13 -04:00
Masahiro Yamada
2846bd03ea ARM: keystone: remove declaration of unused functions
These two functions are neither defined nor referenced.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-07 14:26:35 +00:00
Lokesh Vutla
e2924e5904 ARM: k2g: Configure reset mux to device reset
BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.

Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.

Right now to give a default watchdog behaviour "Device reset" is
being selected.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
2016-06-02 21:42:19 -04:00
Nishanth Menon
2283284b05 ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.

Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
  http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
  http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
  http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
  http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)

Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K    | K2L       | K2E       | K2G
-------+-----------+-----------+-----------+---------
0      | C66x 0    | C66x 0    | C66x 0    | C66x 0
1      | C66x 1    | C66x 1    | Reserved  | ARM
2      | C66x 2    | C66x 2    | Reserved  | ICSS0
3      | C66x 3    | C66x 3    | Reserved  | ICSS1
4      | C66x 4    | Reserved  | Reserved  | NETCP
5      | C66x 5    | Reserved  | Reserved  | CPIE
6      | C66x 6    | Reserved  | Reserved  | USB
7      | C66x 7    | Reserved  | Reserved  | Reserved
8      | ARM       | ARM       | ARM       | MLB
9      | NetCP     | NetCP     | NetCP     | PMMC
10     | QM_PDSP   | QM_PDSP   | QM_PDSP   | DSS
11     | PCIe_0    | PCIe_0    | PCIe_0    | MMC
12     | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13     | Reserved  | Reserved  | PCIe_1    | Reserved
14     | HyperLink | PCIe_1    | HyperLink | Reserved
15     | Reserved  | Reserved  | TSIP      | Reserved
-------+-----------+-----------+-----------+---------

NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.

Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).

By marking these segments as shared, we also ensure SoC wide coherency
is enabled.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:40 -04:00
Nishanth Menon
1f807a9f32 ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.

As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:40 -04:00
Nishanth Menon
705c506e4f ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline function
Fix up BOOT_SET_BITFIELD to be a static inline function to be readable
with the same functionality.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:11 -04:00
Nishanth Menon
f84e8e5b29 ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline function
BOOT_READ_BITFIELD can easily be a static inline function and be a
little more readable with the same functionality.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:11 -04:00
Nishanth Menon
bc69b505f0 ARM: keystone2: Convert BOOTBITMASK to static inline function
BOOTBITMASK is almost impossible to decode, so convert it into a simpler
static line functions of equivalent solution.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-27 09:12:10 -04:00
Tom Rini
aadd3360e6 ARM: keystone2: Split monitor code / command code
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case, we split the code for
supporting the monitor out from the code for loading it.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16 15:03:15 -04:00
Vitaly Andrianov
8efc243741 ARM: keystone2: use detected ddr3a size
Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.

This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.

For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:45 -04:00
Vitaly Andrianov
d9a76e77c8 ARM: keystone2: use SPD info to configure K2HK and K2E DDR3
This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.

The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:44 -04:00
Lokesh Vutla
ef76ebb1ef ARM: keystone2: K2G: Add support for different arm/device speeds
The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:44 -04:00
Lokesh Vutla
5cd1f6bd7a ARM: keystone2: Allow for board specific speed definitions
Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:43 -04:00
Suman Anna
f2a8279e76 ARM: keystone2: K2G: power-off DSP during boot
The DSPs are powered on by default upon a Power ON reset, and
they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E
during the boot in u-boot. This is not functional on K2G though.
Extend the existing DSP power-off support to the only DSP present
on K2G. Do note that the PSC clock domain module id for DSP on K2G
differs from that of previous Keystone2 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:43 -04:00
Suman Anna
4ed8b2c969 ARM: keystone2: Use macro for DSP GEM power domain
Define a macro for the DSP GEM power domain id number and
use it instead of a hard-coded number in the code that
disables all the DSPs on various Keystone2 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:42 -04:00
Nishanth Menon
ec00b2e3ab ARM: keystone2: psc: introduce function to hold and release module in reset.
These are useful for modules that need to be held in reset and are
enabled for data to be loaded on to them. Typically these are
microcontrollers or other processing entities in the system.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:36 -04:00
Nishanth Menon
7ca12b9700 ARM: keystone2: psc-defs: use adequate () for macros
'#define X a | b' is better defined as '#define X (a | b)' for obvious
reasons.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:36 -04:00
Roger Quadros
3b68939fa0 ARM: k2g: add SD card and eMMC support
Add MMC support for k2g

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-10-22 14:22:25 -04:00
Vitaly Andrianov
cddb330035 ARM: k2g: update keystone nav rx queue numbers
update K2G nav rx queue number

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:21 -04:00
Vitaly Andrianov
11d8222a26 ARM: k2g: Correct base addresses
Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO,
and MSMC segments.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:20 -04:00
Vitaly Andrianov
5dd6af2ecb ARM: k2g: Add support for pin mux configuration
Add api for configuring pin mux.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:19 -04:00
Vitaly Andrianov
235dd6e8d1 ARM: k2g: Add ddr3 info
Add ddr3 related info

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:18 -04:00
Vitaly Andrianov
0fba27b690 ARM: k2g: Add PSC info
Add psc information for k2g

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:17 -04:00
Vitaly Andrianov
e6d71e1ca5 ARM: k2g: Add clock information
Add clock information for Galileo

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-10-22 14:22:16 -04:00
Vitaly Andrianov
bda920c65e ARM: k2g: Add pll data
Add pll data for k2g

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:15 -04:00
Lokesh Vutla
f11a328b54 ARM: k2g: Add support for CPU detection
Adding CPU detection support for Keystone2 Galileo.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22 14:22:12 -04:00
Lokesh Vutla
8626cb8021 ARM: k2e/l: Apply WA for selecting PA clock source
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-17 20:16:13 -04:00
Heiko Schocher
92a3188d7d bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11 17:15:32 -04:00
Lokesh Vutla
76b3f195e9 ARM: k2l: Fix device speeds
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue

Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:16 -04:00
Lokesh Vutla
fe772ebd28 ARM: keystone2: Use common definition for clk_get_rate
Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:55 -04:00
Lokesh Vutla
7531122e5c ARM: keystone2: Remove unsed external clocks
Remove unused external clocks and make a common definition
for all keystone platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:54 -04:00
Lokesh Vutla
94069301ba ARM: keystone2: Cleanup init_pll definition
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:53 -04:00
Lokesh Vutla
74af583e9f ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:53 -04:00
Lokesh Vutla
7b50e1599f ARM: keystone2: Fix dev and arm speed detection
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:52 -04:00
Lokesh Vutla
c321a23624 ARM: keystone2: Cleanup PLL init code
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:52 -04:00
Lokesh Vutla
cfe5f0cda0 ARM: keystone2: Cleanup SoC detection
Add proper register definition for JTAG ID and
cleanup cpu_is_* functions.

Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-12 20:47:51 -04:00
Masahiro Yamada
dc7de222aa ARM: keystone: move SoC headers to mach-keystone/include/mach
Move arch/arm/include/asm/arch-keystone/*
  -> arch/arm/mach-keystone/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2015-02-21 08:23:52 -05:00