Commit graph

8 commits

Author SHA1 Message Date
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Michal Simek
866225f394 arm64: xilinx: Move firmware functions from platform to driver
versal_pm_request() and invoke_smc() are almost the same. Only one
difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id.
The patch is moving platform implementation to firmware driver code for
synchronization.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
0f3604a2b3 arm64: versal: Clean pm_api_id usage
Copy enum values from platform code to firmware code. IDs are shared
between ZynqMP and Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Siva Durga Prasad Paladugu
95105089af clk: versal: Add clock driver support
This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:41:24 +02:00
Michal Simek
aef149e9dd arm64: versal: Enable memory mapping via DT
Code reads DT and setup MMU table based on memory node. This will ensure
that only DT needs to be changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:11:14 +02:00
Siva Durga Prasad Paladugu
bfd092f9ca arm64: versal: Define board_late_init for versal
Define board_late_init which performs bootmode detection
and prepares corresponding distro boot commaand sequence.

Also disable it for mini platforms because simply there is no need to have
it enabled.
But also disable it for virtual platform because Qemu is not modelling this
register space that's why travis testing would fail. This configuration
should be reverted when mainline Qemu is updated.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:11:14 +02:00
Siva Durga Prasad Paladugu
4244f2b7e8 arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU
This patch adds new config option which is used for
reserving a specific memory for MMU Table and in this
case we are using TCM for that purpose.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Michal Simek
ec48b6c991 arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:21 +02:00