Commit graph

62 commits

Author SHA1 Message Date
Simon Glass
9368104d2f rockchip: sdram: Tidy up a few comments
Fix spaces in two comments in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
a49dc0a914 rockchip: reset: Use the rk_clr/setreg() interface
Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
0906995bf3 rockchip: sdram: Use the rk_clr/setreg() interface
Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Jeffy Chen
5cc5b901e6 Revert "rockchip: Add max spl size & spl header configs"
This reverts commit 10b4615f9d7e177ec7fe644fbb2616e0e0956f6e

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-13 17:07:06 -07:00
Jeffy Chen
6ae5860942 rockchip: Add max spl size & spl header configs
Our chips may have different max spl size and spl header, so
we need to add configs for that.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
Added $(if...) to tools/Makefile to fix widespread build breakage
Signed-off-by: Simon Glass <sjg@chromium.org>

Series-changes: 8
- Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
- Add $(if...) to tools/Makefile to fix widespread build breakage
2015-12-01 08:07:22 -07:00
huang lin
8117803430 rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig
since different rockchip SOC have different size of SRAM,
So the size SYS_MALLOC_F_LEN may different, so move this
config to rk3288 own Kconfig

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00
Simon Glass
e2e947ff6b rockchip: Add basic support for jerry
This builds and displays an SPL message, but does not function beyond that.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
17aa548ced rockchip: Add basic support for firefly-rk3288
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.

This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
2444dae587 rockchip: Add core SoC start-up code
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
5ff093ab9e rockchip: rk3288: Add SDRAM init
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
13d80ff5af rockchip: rk3288: Add a simple syscon driver
Add a driver that provides access to system controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Simon Glass
3c5d0e34f6 rockchip: rk3288: Add SoC reset driver
We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00