Commit graph

28 commits

Author SHA1 Message Date
Ley Foon Tan
7eece32812 spi: cadence_qspi: Add quad write support
Use quad write if SPI_TX_QUAD flag is set.

Tested quad write on Stratix 10 SoC board (Micron
serial NOR flash, mt25qu02g)

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:03 +05:30
Ley Foon Tan
8b71e46cea spi: cadence_qspi: Fix warning cast from pointer to integer of different size
Use "%p" to print cmdbuf.

Compilation warning as below:

  CC      spl/drivers/spi/cadence_qspi_apb.o
  LD      spl/lib/built-in.o
drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’:
drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
          cmdlen, (unsigned int)cmdbuf);

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-07-12 09:22:11 +02:00
Vignesh R
aaa21d3ffc spi: cadence_qspi_apb: Make flash writes 32 bit aligned
Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.

[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Vignesh R
a743e2ba38 Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"
This reverts commit 57897c13de.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Goldschmidt Simon
948ad4f075 Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
This reverts commit b63b46313e.

This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Jason Rush
15a70a5da3 spi: cadence_spi: Sync DT bindings with Linux
Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-01-24 12:07:50 +05:30
Álvaro Fernández Rojas
48263504c8 wait_bit: use wait_for_bit_le32 and remove wait_for_bit
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Vignesh R
b63b46313e spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:38:35 +01:00
Vignesh R
57897c13de spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.

So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:38:12 +01:00
Phil Edworthy
22e63ff3a2 spi: cadence_qspi: Fix CS timings
The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.

In addition, the existing code does not handle the case when the delay
is less than a SCLK period.

This change accurately calculates the additional delays in Ref clocks.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
3c56953219 spi: cadence_qspi: Remove returns from end of void functions
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
7d403f284c spi: cadence_qspi: Use spi mode at the point it is needed
Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
7e76c4b08a spi: cadence_qspi: Clean up the #define names
A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.

Whilst doing so, also remove the unnecessary brackets around the
constants.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
db37cc9c39 spi: cadence_qspi: Use #define for bits instead of bit shifts
Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.

Whislt at it, fix the names of the "Rd Data Capture" register defs.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
0ceb4d9e9a spi: cadence_qspi: Better debug information on the SPI clock rate
Show what the output clock rate actually is.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
32068c42a7 spi: cadence_qspi: Fix baud rate calculation
With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up the divider to generate
25MHz.

This change fixes the calculation.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Phil Edworthy
cc80a897e4 spi: cadence_qspi: Fix clearing of pol/pha bits
Or'ing together bit positions is clearly wrong.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-12-15 16:57:27 +01:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Chin Liang See
5405817a6e spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value
Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
correct value being written into the register.

Example of the existing bug is when calculated div = 16. After and
with the mask, the value written to register is actually 0 (register
field for baudrate divisor). With this fix, the value written is now
15 which is max value for baudrate divisor.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
2016-08-07 21:54:21 +02:00
Vignesh R
2372e14f19 spi: cadence_quadspi: Enable QUAD mode based on DT data
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-07-09 20:16:33 +05:30
Vignesh R
dac3bf20fb spi: cadence_qspi_apb: Support 32 bit AHB address
AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-07-09 20:16:32 +05:30
Marek Vasut
5a824c493a mtd: cqspi: Simplify indirect read code
The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
2016-05-06 18:41:49 +02:00
Marek Vasut
26da6353e1 mtd: cqspi: Simplify indirect write code
The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.

This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
2016-05-06 18:41:49 +02:00
Jagan Teki
b7e83b087c spi: cadence_qspi_apb: Use BIT macro
Replace numerical bit shift with BIT macro
in cadence_qspi_apb

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27 23:19:29 +05:30
Vikas Manocha
70bb2b1415 spi: cadence_qspi: support FIFO width other than 4 bytes
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Vikas Manocha
90a2f71711 spi: cadence_qspi: get sram size from device tree
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Vikas Manocha
c0535c0ef0 spi: cadence_qspi: move the sram partition in init
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-07-03 13:50:53 +05:30
Stefan Roese
10e8bf88c0 spi: Add Cadence QSPI DM driver used by SoCFPGA
This driver is cloned from the Altera Rockerboard.org U-Boot
repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the
new driver model (DM). One big advantage of this move is that now
multiple SPI drivers can be enabled on one platform. And since the
SoCFPGA also has the Designware SPI master controller integrated,
this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA
to be applied. For DT based probing in the SPI DM.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00