Commit graph

474 commits

Author SHA1 Message Date
Stefan Roese
1bbae2b816 ppc4xx: Remove PCI async bootup message if PCI is not used
Signed-off-by: Stefan Roese <sr@denx.de>
2009-06-12 20:39:52 +02:00
Stefan Roese
d873133f2b ppc4xx: Add Sequoia RAM-booting target
This patch adds another build target for the AMCC Sequoia PPC440EPx
eval board. This RAM-booting version is targeted for boards without
NOR FLASH (NAND booting) which need a possibility to initially
program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
configured to setup the SDRAM, this debugger can load this RAM-
booting image to the target address in SDRAM (in this case 0x1000000)
and start it there. Then U-Boot's standard NAND commands can be
used to program the NAND FLASH (e.g. "nand write ...").

Here the commands to load and start this image from the BDI2000:

440EPX>reset halt
440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
440EPX>go 0x1000000

Please note that this image automatically scans for an already
initialized SDRAM TLB (detected by EPN=0). This TLB will not be
cleared. This TLB doesn't need to be TLB #0, this RAM-booting
version will detect it and preserve it. So booting via BDI2000
will work and booting with a complete different TLB init via
U-Boot works as well.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-06-12 20:39:47 +02:00
Peter Tyser
655b34a78a i2c: Create common default i2c_[set|get]_bus_speed() functions
New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions
replace a number of architecture-specific implementations.

Also, providing default functions will allow all boards to enable
CONFIG_I2C_CMD_TREE.  This was previously not possible since the
tree-form of the i2c command provides the ability to display and modify
the i2c bus speed which requires i2c_[set|get]_bus_speed() to be
present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-06-12 20:39:45 +02:00
Peter Tyser
9c90a2c8e8 i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE value
Many boards/controllers/drivers don't support an I2C slave interface,
however CONFIG_SYS_I2C_SLAVE is used in common code so provide a
default

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-06-12 20:39:45 +02:00
Stefan Roese
399aab7748 ppc4xx: Fix problem with ECC ordering for PPC4xx NDFC platforms
This patch now uses the correct ECC byte order (Smart Media - SMC)
to be used on the 4xx NAND FLASH driver. Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.

Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in
drivers/mtd/nand/nand_ecc.c for correct operation. This is done with
a seperate patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2009-05-23 12:51:39 +02:00
Stefan Roese
5d841fac82 ppc4xx: Move definition for PPC4xx NAND FLASH controller to header
This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2009-05-23 12:51:39 +02:00
Detlev Zundel
792a09eb9d Fix e-mail address of Gary Jennejohn.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-05-15 22:11:59 +02:00
Peter Tyser
f9a109b3ad Replace __attribute references with __attribute__
__attribute__ follows gcc's documented syntax and is generally more
common than __attribute.  This change is only asthetic and should not
affect functionality.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-04-28 01:01:39 +02:00
Stefan Roese
cf9409885c ppc4xx: Add "booting from NAND" to 4xx NAND-booting targets
This additional text in the bootup log helps to see if the board is
configured for NAND-booting. Especially helpful for boards that can
boot from NOR and NAND (e.g. most of the AMCC eval boards).

Signed-off-by: Stefan Roese <sr@denx.de>
2009-04-16 09:12:08 +02:00
Stefan Roese
9cd690160d ppc4xx: Don't write the MAC address into the internal SoC registers
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC
addresses into the SoC registers instead.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-03-20 22:39:14 +01:00
Mike Frysinger
6bacfa6a8e cpu/: get mac address from environment
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.

The cpus that get converted here:
	at91rm9200
	mpc512x
	mpc5xxx
	mpc8260
	mpc8xx
	ppc4xx

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: John Rigby <jrigby@freescale.com>
CC: Stefan Roese <sr@denx.de>
2009-03-20 22:39:11 +01:00
Anatolij Gustschin
f8853d105d ppc4xx: Fix bug in PCI outbound map configuration for canyonlands
PCI outbound address map configuration doesn't match the
PCI memory address range covered by appropriate TLB entry
configuration for canyonlands causing machine check
exceptions while accessing PCI memory regions. This patch
provides a fix for this issue.

Kazuaki Ichinohe observed and reported this issue while
testing display output with PCI ATI video card on canyonlands.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-03-20 12:58:31 +01:00
Stefan Roese
b4996d6b21 ppc4xx: PCIe: Change 16GB inbound memory to 4GB
This patch fixes a problem recently seen on some 4xx platforms. For
example on Kilauea PCIe slot #0.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-18 15:59:20 +01:00
Carolyn Smith
7369f0e384 ppc4xx: Fix initialization of the SDRAM_CODT register
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.

Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-12 06:15:48 +01:00
Adam Graham
c645012aef ppc4xx: Autocalibration can set RDCC to over aggressive value.
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.

On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".

This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.

The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.

The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration.  The default will be the
"T2 Sample" value.  A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".

Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-12 06:08:07 +01:00
Kumar Gala
87c9063963 ppc: Move CONFIG_MAX_MEM_MAPPED to common config.h
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
between the two current users (lib_ppc/board.c, 44x SPD DDR2).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
2009-02-10 00:44:13 +01:00
Kumar Gala
ff4e66e93c pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.

Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-07 23:50:04 +01:00
Dirk Eibach
59d1bda7f9 ppc4xx: Make PCIE support selectable
On some platforms PCIE support is not required, but would be included
because the cpu supports it. To reduce fooprint it is now configurable
via CONFIG_PCI_DISABLE_PCIE.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-06 11:06:19 +01:00
Matthias Fuchs
b129eff5ed ppc4xx: Only fixup opb attached UARTs
This patch updates the fdt UART clock fixup code to
only touch CPU internal UARTs on 4xx systems.
Only these UARTs are definitely clocked by gd->uart_clk.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-02-06 10:53:15 +01:00
Peter Tyser
62c3ae7c6e Standardize command usage messages with cmd_usage()
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-28 08:43:45 +01:00
Dirk Eibach
3943d2ff6c ppc4xx: Improve DDR autodetect
Added support for a second memory bank to DDR autodetection for 440
platforms.
Made hardcoded values configurable.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-26 10:13:11 +01:00
Wolfgang Denk
455ae7e87f Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-16 01:02:17 +01:00
Timur Tabi
ecf5f077c8 i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-15 23:46:21 +01:00
Trent Piepho
5e3ab68e9a Section name should be ".data", not "data"
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-09 00:48:41 +01:00
Peter Tyser
561858ee7d Update U-Boot's build timestamp on every compile
Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-06 23:36:43 +01:00
Dave Mitchell
ddf45cc758 ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 11:02:04 +01:00
Dave Mitchell
b14ca4b61a ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 10:52:33 +01:00
Stefan Roese
25fb4eaaea ppc4xx: Clear all potentially pending exceptions in MCSR
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().

Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-20 11:48:53 +01:00
Ben Warren
25a859066b Moved initialization of PPC4xx EMAC to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:05 -08:00
Ben Warren
4d03a4e20e Moved PPC4xx EMAC driver to drivers/net
Also changed path in all linker scripts that reference this driver

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:04 -08:00
Ben Warren
96e21f86e8 Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMAC
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:04 -08:00
Ricardo Ribalda Delgado
1f4d53260e ppc4xx: Generic architecture for xilinx ppc405(v3)
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:26:09 +02:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Adam Graham
c9c11d751e ppc4xx: Add routine to retrieve CPU number
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's.  Default behavior
is the existing single CPU print output.  Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:56 +02:00
Adam Graham
59217bae40 ppc4xx: Add static support for 44x IBM SDRAM Controller
This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:51 +02:00
Wolfgang Denk
8ed44d91c8 Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:39 +02:00
Markus Klotzbuecher
50bd0057ba Merge git://git.denx.de/u-boot into x1
Conflicts:

	drivers/usb/usb_ohci.c
2008-10-21 09:18:01 +02:00
Wolfgang Denk
f82642e338 Merge 'next' branch
Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18 21:59:44 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Yuri Tikhonov
bf29e0ea0a ppc4xx: PPC44x MQ initialization
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.

Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-17 13:02:42 +02:00
Remy Bohmer
9dbc366744 The PIPE_INTERRUPT flag is used wrong
At a lot of places in the code the PIPE_INTERRUPT flags and friends
are used wrong. The wrong bits are compared to this flag resulting
in wrong conditions. Also there are macros that should be used for
PIPE_* flags.
This patch tries to fix them all, however, I was not able to test the
changes, because I do not have any of these boards.

Review required!

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
2008-10-14 16:43:06 +02:00
Adam Graham
f8a00dea84 ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-08 11:36:23 +02:00
Stefan Roese
023824549a Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)"
This reverts commit 3eec160a3a.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-22 11:06:50 +02:00
Victor Gallardo
3eec160a3a ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-16 20:16:31 +02:00
Stefan Roese
7bf5ecfa50 ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].

The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-12 07:12:33 +02:00
Stefan Roese
f071f01fd0 ppc4xx: Remove CONFIG_CS8952_PHY define
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:56 +02:00
Stefan Roese
6ca8646c18 ppc4xx: Fix compilation warning for PIP405
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:51 +02:00
Stefan Roese
725b53ac61 ppc4xx: Fix compilation warning for canyonlands & glacier
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:46 +02:00
Victor Gallardo
78d7823689 ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.

Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:21:16 +02:00