Commit graph

601 commits

Author SHA1 Message Date
Tom Rini
4c7df3b184 arm: rk3368: Select ARCH_EARLY_INIT_R when used
On the lion and evb-px5 platforms, we need this function, so select it.

Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Cc: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-03-02 15:32:25 -05:00
Simon Glass
ce119a2706 Correct SPL uses of ROCKCHIP_OTP
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ROCKCHIP_OTP defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
41782a9c09 Correct SPL uses of FASTBOOT
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
3c9adeb330 Correct SPL uses of ROCKCHIP_EFUSE
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ROCKCHIP_EFUSE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
f27a545b8f Correct SPL use of DISPLAY_CPUINFO
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_DISPLAY_CPUINFO defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:26 -05:00
Simon Glass
799e5be706 Correct SPL use of CMD_NET
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_CMD_NET defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:26 -05:00
Simon Glass
784d4fdfdb rockchip: Correct a reference to CONFIG_BOOT_MODE_REG
This option does not exist and should refer to
CONFIG_ROCKCHIP_BOOT_MODE_REG instead. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-07 14:33:48 -05:00
Tom Rini
6e7df1d151 global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-20 12:27:24 -05:00
Simon Glass
12c3e948ee rockchip: Drop the FIT generator script
This is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 14:55:40 -07:00
Simon Glass
b2412dd5de rockchip: Enable bootstage on rockpro64
This board is useful for benchmarking overall U-Boot performance. Enable
the bootstage feature so we get a report.

Since this returns to the boot rom before finishing executing
board_init_r() in SPL, add a few bootstage calls so that we can collect
timing from TPL.

For the stash region, use a portion of SRAM, 64KB below the stack top.
This allows the TPL image to be up to nearly 120KB (it is typically about
64KB). SPL normally runs from SDRAM at 0, so can use the same stash
region.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-18 11:49:13 -07:00
Quentin Schulz
c925be73a0 rockchip: add support for PX30 Ringneck SoM on Haikou Devkit
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip
PX30 in a micro Qseven-compatible form-factor.

PX30-µQ7 features:
        * CPU: quad-core Cortex-A35
        * DRAM: 2GB dual-channel
        * eMMC: onboard eMMC
        * SD/MMC
        * TI DP83825I 10/100Mbps PHY
        * USB:
                * USB2.0 dual role port
                * 3x USB2.0 host via onboard USB2.0 hub
        * Display: MIPI-DSI
        * Camera: MIPI-CSI
        * onboard 2.4GHz WiFi + Bluetooth module
        * Companion Controller: on-board additional microcontroller
	  (STM32 Cortex-M0 or ATtiny):
                * RTC
                * fan controller
                * CAN (only STM32)

The non-U-Boot DTS files are imported from Linux v6.2-rc2.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
600e0177e7 rockchip: px30: insert u-boot, spl-boot-device into U-Boot device tree
It is possible to boot U-Boot proper from a different storage medium
than the one used by the BOOTROM to load the SPL. This information is
stored in the u-boot,spl-boot-device Device Tree property and is
accessible from U-Boot proper so that it has knowledge at runtime where
it was loaded from.

Let's add support for this feature for px30.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
3898237384 rockchip: px30: list possible SPL boot devices
BOOTROM sets a bit in a CPU register so that the software can know from
where the first stage bootloader was booted. One use case for this is to
specify the default loading medium for U-Boot proper to match the one
used by the BOOTROM to load the SPL (same-as-spl in
u-boot,spl-boot-order).

Let's create the mapping between BOOTROM value and Device Tree node
names for MMC devices.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-16 18:01:11 +08:00
Quentin Schulz
e53856aaf4 rockchip: px30: fix possibly unused grf and cru variables
The grf and cru are only used when no UART base is provided by the user
(defaults to UART2) or for UART1, UART3 and UART5 to be used for the
debug UART. Therefore, let's surround those variable definitions with
the proper checks.

This wasn't an issue before support for UART0 was added, because all
cases were using cru and grf. UART0 only uses pmucru so there's a need
to not define those variables anymore.

Fixes: d0af506625 ("rockchip: px30: support debug uart on UART0")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Peter Robinson
5a42fd0258 rockchip: Add initial support for the PINE64 Pinephone Pro
The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.

Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-16 18:01:11 +08:00
Jagan Teki
b8f1ca9540 board: rockchip: Add Edgeble Neu2 IO Board
Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-01-16 18:01:11 +08:00
Jagan Teki
c6154677c8 arm: rockchip: rv1126: Set dram area unsecure for SPL
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:11 +08:00
Jagan Teki
ffb191e458 arm: rockchip: Add RV1126 arch core support
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04
2023-01-16 18:01:11 +08:00
Quentin Schulz
4b56446002 rockchip: px30: make watchdog and tsadc trigger a first global reset
By default, the PX30 is configured for watchdog and tsadc to trigger a
second global reset which is a more permissive reset than first global
reset.

From TRM part 1 "2.3 System Reset Solution":
glb_srstn_1 will reset the all logic, and
glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs.

This enforces that the watchdog and tsadc trigger glb_srstn_1 as
similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?),
TF-A and Coreboot.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16 18:01:10 +08:00
Tom Rini
957848882c rk32xx: Use standard TPL linker script
As of 2f41ade79e ("linker: Modify linker scripts to be more generic")
we can use the same linker script for SPL and TPL and not have to make
use of #undef tricks. Remove these last remnants.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23 10:07:03 -05:00
Tom Rini
14f43797d0 Prepare v2023.01-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmOgaw0ACgkQFHw5/5Y0
 tyxIeQv8DfAAB8hN+wWeDhQAJBXBLvV+RrocGJ2lpuWN0DUgT955l0zSjP4eD5I/
 sSsT8iJ15obkbWHq61V9W81Velw5qR+gHW9IAzFKiQBfvdcdfgWFeme9fWp/gqxn
 vvPc2sULA9utkc+kQ+qJy2hmTM7I0ZbKzUwTXSv+Tp9on3vlc0quKSHiZ1EvHNww
 8tW13d1r+Be+CC+GVPrhJojfKBcYVJhW21rJMgb4JdfGNWKmpUpF6fUzHe0wiy2P
 HSnScr44E099t9RDZabw0V1fEgQqxIAmL1qQamXf9ddLZQM9Sq63lygTtGsqg61+
 qeHCZVjPg9cXayGfRVesH8sko3vW+IPuo0Q6Ox0vAyRSyzTpOcTuzn3RcMrq+mfu
 ZRF32aFJKVvAI3xesOj1aCBBYjl4POiHA8i3yeP9KcjqW3So0aphDtxp1idgwOZl
 kIxuC4ItWyF7xoyng/7RWwr2VjcKSyw58stRjfV+WNcByV4+ud1A59vsgZOqO49m
 0bLx5dGu
 =EX/F
 -----END PGP SIGNATURE-----

Merge tag 'v2023.01-rc4' into next

Prepare v2023.01-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-21 13:09:01 -05:00
Sughosh Ganu
bea9267d7e rockchip: capsule: Add functions for supporting capsule updates
Add functions needed to support the UEFI capsule update feature on
rockchip boards. Currently, the feature is being enabled on the
RockPi4 boards with firmware images residing on GPT partitioned
storage media.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Tom Rini
aa6e94deab global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-31 11:01:31 -04:00
Quentin Schulz
d0af506625 rockchip: px30: support debug uart on UART0
UART0 can obviously also be used for debug uart in U-Boot, so let's add
its support.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Quentin Schulz
d774b2651a rockchip: rk3399: fix incorrect ifdef check on SPL_GPIO
The check to perform is on CONFIG_SPL_GPIO and not SPL_GPIO.
Because this was never compiled in, it missed an include of cru.h that
was not detected before. Let's include it too.

Also switch to IS_ENABLED in-code check as it is the preferred
inclusion/exclusion mechanism.

Fixes: 07586ee432 ("rockchip: rk3399: Support common spl_board_init")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Quentin Schulz
3a61ee7fae rockchip: rk3399: fix incorrect ifdef check on SPL_DM_REGULATOR
The check to perform is on CONFIG_SPL_DM_REGULATOR and not
SPL_DM_REGULATOR. Also switch to in-code check instead of ifdefs.

Fixes: 07586ee432 ("rockchip: rk3399: Support common spl_board_init")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> # Rock960
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Johan Jonker
f9c68a566c rockchip: phycore_rk3288: remove phycore_init() function
The phycore_rk3288 board has a SPL size problem,
so remove phycore_init() function to stay within the limits.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19 19:30:48 +08:00
Pali Rohár
049704f808 board_f: Fix types for board_get_usable_ram_top()
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.

So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.

Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23 15:12:42 -04:00
Quentin Schulz
a4bb36df49 rockchip: allow to build SPI images even without HAS_ROM option
This prepares for the creation of a u-boot-rockchip-spi.bin image
similar to u-boot-rockchip.bin to the exception it's destined for
SPI-NOR flashes instead of MMC storage medium.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:39 +08:00
Quentin Schulz
7a81a44caf rockchip: rk3399: sync spl_boot_devices_tbl and boot_devices node paths
While technically not a bug, let's have some consistency in paths
returned by u-boot,spl-boot-order look-up and the one saved in
u-boot,spl-boot-device by syncing spl_boot_devices_tbl and boot_devices
node paths.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:39 +08:00
Quentin Schulz
72ebe8b8cb rockchip: rk3399: fix incorrect boot-device in u-boot, spl-boot-device
On RK3399, mmc0 is eMMC and mmc1 is SD card, c.f. console:
MMC:   mmc@fe320000: 1, mmc@fe330000: 0

In arch/arm/mach-rockchip/spl-boot-order.c:board_boot_order, the
boot_device (BOOT_DEVICE_*) value is gotten from spl_node_to_boot_device
function. Said function returns BOOT_DEVICE_MMC1 for mmc0 (eMMC) and
BOOT_DEVICE_MMC2 for mmc1 (SD card).

Since the SD card controller is at mmc@fe320000, it should be associated
with BOOT_DEVICE_MMC2 and not BOOT_DEVICE_MMC1. Same applies to eMMC.

Let's fix that by swapping the two BOOT_DEVICEs.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
2022-09-04 20:00:38 +08:00
John Keeping
74f7025ea6 rockchip: rk3308: fix same-as-spl boot order
Rockchip SoCs need the boot_devices array defined in order to map the
bootloader's value to a U-Boot device.  Implement this for rk3308.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:38 +08:00
Quentin Schulz
07b5d348a6 rockchip: rk3399: boot_devices: fix eMMC node name
When idbloader.img is flashed on the eMMC, the SPL still tries to load
from SPI-NOR first.

This is due to an incorrect look-up in the Device Tree. Since commit
822556a934 ("arm: dts: sync the Rockhip 3399 SoCs from Linux"), the
node name (but not label) changed from sdhci@fe330000 to mmc@fe330000
meaning U-Boot SPL is not looking for the correct node name anymore and
fails to find the "same-as-spl" node when eMMC is the medium from which
the SPL booted.

Fixes: 822556a934 ("arm: dts: sync the Rockhip 3399 SoCs from Linux")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Artem Lapkin  <email2tema@gmail.com>
Tested-by: Artem Lapkin  <email2tema@gmail.com>
Tested-by: Lapkin Artem <email2tema@gmail.com>
Tested-by: Lapkin Artem <email2tema@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04 20:00:38 +08:00
Tom Rini
36b661dc91 Merge branch 'next' 2022-07-11 14:58:57 -04:00
Chris Morgan
30975fb73d rockchip: Add option to prevent booting on power plug-in
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-29 11:42:10 +08:00
Jerome Forissier
348310233d mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.

Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.

With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].

Link: [1] 5dd1570ac5
Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-29 11:32:35 +08:00
Johan Jonker
e0479b71ed rockchip: board: change condition board_usb_init() in function
Change define condition in board_usb_init() function
to allow rk3066/rk3188 to use the USB PHY driver.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:16 +08:00
Tom Rini
5858b90f50 spl: Move SPL_LDSCRIPT defaults to one place
We want to keep all of the default values for SPL_LDSCRIPT in the same
place both for overall clarity as well as not polluting unrelated config
files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-28 17:03:31 -04:00
Andrew Scull
99e2fbcb69 linker_lists: Rename sections to remove . prefix
Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.

Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.

Signed-off-by: Andrew Scull <ascull@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-23 12:58:18 -04:00
Tom Rini
ca8a329a1b Convert CONFIG_SPL_PAD_TO et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_PAD_TO
   CONFIG_SPL_MAX_SIZE
   CONFIG_TPL_PAD_TO
   CONFIG_TPL_MAX_SIZE

Note that we need to make TPL_MAX_SIZE be hex, and so move and convert the
existing places.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:06 -04:00
Peng Fan
151a030063 arm: set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is valid
Since COUNTER_FREQUENCY is obselete, so set cntfrq_el0 if
CONFIG_COUNTER_FREQUENCY is valid

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2022-04-21 15:27:18 -04:00
Johan Jonker
5859bb2863 rockchip: fix boot_devices constants
The DT node name pattern in mmc-controller.yaml for mmc
is "^mmc(@.*)?$". The Rockchip mmc nodes have been synced
with Linux, so update the boot_devices constants as well.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Johan Jonker
62fcd72ef2 rockchip: rk3066: add Rikomagic MK808 board
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port,
HDMI and a micro-SD card slot. It also includes on-board NAND
and 1GB of SDRAM.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Johan Jonker
33f4750783 rockchip: rk3066: add core support
Add the core architecture code for the rk3066.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Johan Jonker
30a7b824aa rockchip: tpl: use IS_ENABLED for timer_init() call condition
Not all Rockchip SoC models use the ARM arch timer.
Call the function timer_init() only when
CONFIG_SYS_ARCH_TIMER is available.
Use the call condition IS_ENABLED to increase
build coverage and make the code easier to read.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Johan Jonker
d23f55d217 rockchip: tpl: change call condition rockchip_stimer_init()
The Rockchip SoCs rk3066/rk3188 have no CONFIG_ROCKCHIP_STIMER_BASE
defined. Currently there's no exception in TPL. Make this more
generic and compile the code inside the function rockchip_stimer_init()
only when CONFIG_ROCKCHIP_STIMER_BASE is available.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Johan Jonker
12a716422f rockchip: spl: change call condition rockchip_stimer_init()
The Rockchip SoCs rk3066/rk3188 have no CONFIG_ROCKCHIP_STIMER_BASE
defined. Currently only rk3188 has an exception in SPL. Make this more
generic and compile code inside the function rockchip_stimer_init()
only when CONFIG_ROCKCHIP_STIMER_BASE is available.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:12 +08:00
Johan Jonker
54562045e5 rockchip: move ROCKCHIP_STIMER_BASE to Kconfig
Move ROCKCHIP_STIMER_BASE to Kconfig.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:12 +08:00
Andre Przywara
5907357322 spl: mmc: extend spl_mmc_boot_mode() to take mmc argument
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.

Pass the pointer to the mmc struct to that function, so implementations
can make use of that.

Compile-tested for all users changed.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA)
Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3)
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-04 23:24:17 +01:00