Enable all logging features on sandbox so that the tests can be run.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful to display log messages on the console. Add a simple driver
to handle this.
Note that this driver outputs to the console, which may be serial or
video. It does not specifically select serial output.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This does not appear to be used by any boards. Before introducing a new
log system, remove this old one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With clang this gives a warning because hubsts appears to be used before
it is set, even if ultimately it is not used. Simplify the code to avoid
this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
The debug() macro now evaluates its expression so does not need #ifdef
protection. In fact the current code causes a warning with the new log
implementation. Adjust the code to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Before adding new features, move these definitions to a separate header
to avoid further cluttering common.h.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
While sandbox works OK without the special-case code, it does result in
console output being stored in the pre-console buffer while sandbox starts
up. If there is a crash or a problem then there is no indication of what
is going on.
For ease of debugging it seems better to revert this change also.
This reverts commit d8c6fb8ced.
Signed-off-by: Simon Glass <sjg@chromium.org>
We cannot use sandbox memory at 0 since other things use memory at that
address. Move it up out of the way.
Note that the pre-console buffer is currently disabled with sandbox, but
this change will avoid confusion if it is manually enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
While sandbox works OK without the special-case code, it does result in
console output being stored in the pre-console buffer while sandbox starts
up. If there is a crash or a problem then there is no indication of what
is going on.
For ease of debugging it seems better to revert this change.
This reverts commit 47b98ad0f6.
Signed-off-by: Simon Glass <sjg@chromium.org>
The A33-OLinuXino defconfig was using the default CONS_INDEX value for
A33, which actually points to the R_UART, which is routed to the GPIO
header without proper pull-ups or diodes. The board has a separate
header for UART0, which are routed to pins PB0 and PB1. This header
is properly marked and is likely the first pins any user would try
to get a console.
Fix CONS_INDEX in the defconfig so the console appears on UART0.
Fixes: ca5c37026b ("sunxi: Add support for A33-OLinuXino board")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Now that more and more devices are built using eMMC, providing a way to
easily flash the system without too much hassle seems like a right thing to
do.
Since fastboot is the most deployed tool to do that these days, we can just
rely on it to provide a way to flash the various components in the system
(SPL, U-Boot and the system itself) easily, especially since you can upload
the U-Boot hosting the fastboot "server" through FEL.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The partitions variable is especially useful to create a partition table
from U-Boot, either directly from the U-Boot shell, or through flashing
tools like fastboot and its oem format command.
This is especially useful on devices with an eMMC you can't take out to
flash from another system, and booting a Linux system first to flash our
system then is not really practical.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The SPL must be located at 8kB (16 sectors) offset. That's right in the
middle of the GPT, so we need to define a smaller amount of partitions to
accomodate for that location.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On some SoCs, the SPL needs to be located right in the middle of the GPT
partition entries.
One way to work around that is to create partition entries for a smaller
number of partitions to accomodate with where the SPL will be. Create a
Kconfig option to allow to do that.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
sdram sub command of i2c command does not support Drivers Model.
This adds Drivers Model support to sdram sub command.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
The .probe_chip function is supposed to probe an i2c device on the bus to
determine whether a device is answering to a particular address.
at91_i2c_probe_chip() did not do anything resembling this and always
returned 0.
It looks as though at91_i2c_probe_chip() was intended to be a .probe
function for the controller, as it was copied-and-pasted to become
at91_i2c_probe() in 0bc8f640a4.
Removing the at91_i2c_probe_chip() function makes the higher layer
(i2c_probe_chip()) try a zero-length read transfer to test for the
presence of a device instead, which does work.
Signed-off-by: Alan Ott <alan@softiron.com>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The driver must wait for TXRDY after each byte is pushed into
the i2c FIFO before pushing the next byte. Previously this was
not done for the first byte, causing a race condition with zeros
sometimes being sent for the next byte (which is typically the
first actual data byte).
Signed-off-by: Alan Ott <alan@softiron.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add some comment describing the purpose of struct members and
functions.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Change meson_i2c_xfer_msg() to return -EREMOTEIO in case of NACK, as
done by other drivers. Also, don't change the return error in
meson_i2c_xfer().
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
The datasheet doesn't specify a suggested timeout and 500ms seems very
long: reduce it to 100ms.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
>From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For case when MC is loaded but DPL is not deployed perform MC
object [DPBP, DPIO, DPNI and DPRC] cleanup.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add fall back option, to boot from NOR/QSPI/SD for LS1043, LS1046,
LS1021 in case of distro boot failure.
For LS1046, add kernel validation in case of secure boot in sd_bootcmd
and qspi_bootcmd. For LS1043 and LS1021, add kernel validation in case
of secure boot in sd_bootcmd, qspi_bootcmdand nor_bootcmd.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Adds config CONFIG_FSL_LS_PPA and CONFIG_FSL_CAAM in
LS2080AQDS and LS2080ARDB secure boot defconfig.
Removes CONFIG_FIT, as with CONFIG_FSL_LS_PPA enabled,
CONFIG_FIT is selected.
Removes CONFIG_SPL_RSA as in NOR boot SPL boot is not done.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add the secure boot defconfigs for QSPI boot on LS1088ARDB
and LS1088AQDS platforms.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC
phase using esbc_validate command.
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment
Add header address for PPA to be validated during ESBC phase for
LS1088A platform based on LAyerscape Chasis 3.
Moves sec_init prior to ppa_init as for validation of PPA sec must
be initialised before the PPA is initialised.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Kernel is now located at 0x1000000 instead of 0xa00000
and envirorment variables are located at 3MB offset instead of
2MB in Flash.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This is suplement for patch which handle below errata:
A-009007, A-009008, A-008997, A-009798
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Instruction prefetch feature is by default enabled during core
release. This patch add support of disabling instruction prefetch
by setting core mask in PPA. Here each core mask bit represents a
core and prefetch is disabled at the time of core release.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IFC-NOR and QSPI-NOR signals are muxed on SoC to save pins
Add fsl_fdt_fixup_flash() to disable IFC-NOR node in dts
if QSPI is enabled and vice-versa
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Existing MC driver framework is based on MC-9.x.x flib. This patch
migrates MC obj (DPBP, DPNI, DPRC, DPMAC etc) to use latest MC flib
which is MC-10.3.0.
Changes introduced due to migration:
1. To get OBJ token, pair of create and open API replaces create APIs
2. Pair of close and destroy APIs replaces destroy APIs
3. For version read, get_version APIs replaces get_attributes APIs
4. dpni_get/reset_statistics APIs replaces dpni_get/set_counter APIs
5. Simplifies struct dpni_cfg and removes dpni_extended_cfg struct
6. Single API dpni_get_buffer_layout/set_buffer_layout replaces
dpni_get_rx/set_rx, tx related, tx_conf_buffer_layout related APIs.
New API takes a queue type as an argument.
7. Similarly dpni_get_queue/set_queue replaces
dpni_get_rx_flow/set_rx_flow , tx_flow related, tx_conf related
APIs
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Unset USE_BOOTCOMMAND for all ls1088 defconfig files to fix
redefinition error. USE_BOOTCOMMAND was introduced in commit
b6251db8c3 ("Kconfig: Introduce USE_BOOTCOMMAND and migrate
BOOTCOMMAND").
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.
Signed-off-by: York Sun <york.sun@nxp.com>
This issue is exposed after commit 9000eddbae ("drivers/usb/ehci:
Use platform-specific accessors"), the wrong endianness of EHCI
controller programing will cause USB function down.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This issue is exposed after commit 9000eddbae ("drivers/usb/ehci:
Use platform-specific accessors"), the wrong endianness of EHCI
controller programing will cause USB function down.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Since commit 2614a20847 ("common: command: tempory buffer should
have size of command line buf"), there have been consistent Travis CI
failures on my builds (interestingly not for Tom, even though building
the same commit id) due to a SEGV in building the byteswapped
omapimage:
arm: pcm051_rev3
make[2]: *** [MLO.byteswap] Error 139
^^^ error code for a SEGV
Turns out that the word-based byte-swapping loop in omapimage.c is to
blame. With the loop condition
while (swapped <= (sbuf->st_size / sizeof(uint32_t)))
there had been one-too-many iterations for all file sizes divisible by
the sizeof(uint32_t). I.e. we had 1 iteration for 0 bytes (and also 1
through 3 bytes) and 2 iterations at 4 bytes... clearly overshooting
on 0 and 4 bytes.
This commit fixes the calculation of an up-rounded word-count and
makes sure to keep the zero-based loop-counter below the number of
words to be processed.
References: 2614a20 ("common: command: tempory buffer should have size of command line buf")
Fixes: 79b9ebb ("omapimage: Add support for byteswapped SPI images")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Martin Elshuber <martin.elshuber@theobroma-systems.com>
Commit f5a2a93892 ("efi_loader: consistently use efi_uintn_t in boot
services") changed the internal EFI API header without adapting its existing
EFI stub users. Let's adapt the EFI stub as well.
Fixes: f5a2a93892 ("efi_loader: consistently use efi_uintn_t in boot services")
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Odroid HC1 board is based on Odroid XU4 board, but it has no HDMI,
no eMMC, no build-in USB3.0 hub, no extension port pins, and no GPIO
button. USB3.0 ports are used for build-in JMicron USB to SATA bridge
and Gigabit R8152 ethernet chips. HC1 uses only passive cooling.
This patch also updates Odroid's ADCmax array and reduces ADC tolerance
to 1% to ensure that XU4 and HC1 revisions are properly detected.
I've tested this with XU3, XU3-lite, XU4 and HC1 boards. In case of my test
boards I got following values from ADC register: 372, 370, 1281 and 1313.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
After updating dtc-1.4.5 version, there are too many warning.
This patch is to fix about exynos4 series.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
