Commit graph

4 commits

Author SHA1 Message Date
Zong Li
835210a125 board: sifive: use ccache driver instead of helper function
Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07 10:34:29 +08:00
Pragnesh Patel
5ce50206ed riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03 15:09:06 +08:00
Pragnesh Patel
01cdef22ee riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.

SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
7c45fc9870 riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00