Commit graph

61828 commits

Author SHA1 Message Date
Marek Vasut
a1a9843a29 ARM: socfpga: Unreset NAND in SPL on Gen5
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP
explicitly in the platform code as the denali-spl driver is not aware
of DM at all.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
533832c6a4 ARM: socfpga: Introduce u-boot-with-nand-spl.sfp target
The NAND devices with 128 kiB erase blocks require extra 64 kiB padding
between each SPL image. Generate U-Boot image with such a padding using
this new target.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
2007a730ee ARM: socfpga: Add ArriaV ST/SX ID
Add new FPGA ID for ArriaV ST/D3 or SX/B3 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
97a72bc286 ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.

When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba <------- this is in fact a value which is stored in
                            a memory at 0xff200000
=> bridge enable ; md 0xff200000 1
ff200000: 90effe09 <------- this is in fact a value which is stored in
                            a memory at 0xff200010
and so it continues. Issuing a write does lock the system up completely.

This patch opens the FPGA bridges in 'bridge enable' command, the tears
them down again, and then opens them again. This allows these outstanding
transactions to complete and makes this misbehavior go away.

However, it is not entirely clear whether this is the correct solution.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
446cf811c5 ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register,
which releases all bridges from reset, instead of putting all bridges
into reset. Fix this by inverting the mask and actually putting the
bridges into reset.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-25 13:12:55 +01:00
Yinbo Zhu
3fca56ee42 configs: enable eSDHC device module for T4240RDB board
Enable eSDHC device module for T4240RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:28 +05:30
Yinbo Zhu
356152fd94 configs: enable eSDHC device module for T2080RDB board
Enable eSDHC device module for T2080RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:28 +05:30
Yinbo Zhu
830e46528e configs: enable eSDHC device module for T1042D4RDB board
Enable eSDHC device module for T1042D4RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:28 +05:30
Yinbo Zhu
26532cab65 configs: enable eSDHC device module for T1024RDB board
Enable eSDHC device module for T1024RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:28 +05:30
Yinbo Zhu
9eb7ed194d configs: enable eSDHC device module for P5040DS board
Enable eSDHC device module for P5040DS board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:28 +05:30
Yinbo Zhu
6a41f77e24 configs: enable eSDHC device module for P4080DS board
Enable eSDHC device module for P4080DS board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
2e83e80094 configs: enable eSDHC device module for P3041DS board
Enable eSDHC device module for P3041DS board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
83309ef3d8 configs: enable eSDHC device module for P2041RDB board
Enable eSDHC device module for P2041RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
02504ef07e configs: enable eSDHC device module for P2020RDB board
Enable eSDHC device module for P2020RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
20186d071e configs: enable eSDHC device module for P1020RDB board
Enable eSDHC device module for P1020RDB board

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
7e20c1f4b1 board: sdhc: Use block layer to read from mmc
Use block layer to read from mmc

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
c44d05d97b arch: powerpc: add eSDHC node to t4240 dts
Add eSDHC node to t4240 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
3f8f668d8c arch: powerpc: add eSDHC node to t104x dts
Add eSDHC node to t104x dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
d2c398b75f arch: powerpc: add eSDHC node to t102x dts
Add eSDHC node to t102x dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
428e7a1da6 arch: powerpc: add eSDHC node to p5040 dts
Add eSDHC node to p5040 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
9d05cd2ae9 arch: powerpc: add eSDHC node to p4080 dts
Add eSDHC node to p4080 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
dfeb70c182 arch: powerpc: add eSDHC node to p3041 dts
Add eSDHC node to p3041 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
067e09f23f arch: powerpc: add eSDHC node to p2041 dts
Add eSDHC node to p2041 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Yinbo Zhu
e126363dc7 arch: powerpc: add eSDHC node to p2020 dts
Add eSDHC node to p2020 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Yinbo Zhu
b73d5379c5 arch: powerpc: add eSDHC node to p1020 dts
Add eSDHC node to p1020 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Fabio Estevam
beeb57f0a6 Revert "video: mxsfb: Configure the clock after eLCDIF reset"
Commit ec3dcea744 ("video: mxsfb: Configure the clock after eLCDIF reset")
causes boot regression on imx7d-pico/imx7d-sdb boards, so revert it
until a better solution is prepared.

This reverts commit ec3dcea744.

Reported-by: Joris Offouga <offougajoris@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-11-24 21:50:44 +01:00
Matthias Brugger
5694090670 ARM: defconfig: add unified config for RPi3 and RPi4
Provide a defconfig which allows us to boot Raspberrry Pi 4
and Raspberry Pi 3 Model B/B+
Instead of using the embedded DTB as done in RPi3 we use the
devicetree provided by the firmware.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:28 +01:00
Matthias Brugger
917a1e9a78 ARM: bcm283x: Set memory map at run-time
For bcm283x based on arm64 we also have to change the mm_region.
Add assign this in mach_cpu_init() so we can create now one binary
for RPi3 and RPi4.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:28 +01:00
Matthias Brugger
dd47ca7873 ARM: bcm283x: Set rpi_bcm283x_base at run-time
As part of the effort to create one binary for several bcm83x SoCs
we read the IO base address from device-tree.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
8e3361c88a ARM: bcm283x: Move BCM283x_BASE to a global variable
We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
37964494c0 rpi: push fw_dtb_pointer in the .data section
The fw_dtb_pointer was defined in the assembly code, which makes him
live in section .text_rest
Put that's not necessary, we can push the variable in the .data section.

This will prevent relocation errors like:
board/raspberrypi/rpi/rpi.c:317:(.text.board_get_usable_ram_top+0x8):
relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol
`fw_dtb_pointer' defined in .text section in board/raspberrypi/rpi/built-in.o

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
3f8b8e3036 drivers: bcm283x: Set pre-location flag for OF_BOARD
U-Boot support on Raspberry Pi 4 relies on the device-tree
provided by the firmware. The blob does not contain the
U-Boot specific pre-loc-rel properties. The result is, that
the U-Boot banner is not printed.

We fix this by setting the DM_FLAG_PRE_RELOC flag in the driver,
if we rely on a device-tree provided by the firmware.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
5051377a0b arm: dts: bcm283x: Rename U-Boot file
Rename the file bcm283x-uboot.dtsi so that it get
automatically include through the scripts/Makefile.lib
using $(CONFIG_SYS_SOC))-u-boot.dtsi

Without this uarts and pincontroller miss the property dm-pre-reloc
and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails
as the pins are not set correctly.
As a result the U-Boot banner isn't shown on boot.

Before commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we included bcm283x-uboot.dtsi directly in the device-tree file.
Which got deleted by the metioned commit.
This is a much robuster solution.

Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
89e47e8eb6 fdt: fix bcm283x dm-pre-reloc definitions
In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we deleted the label for the node soc from bcm283x.dtsi

As we don't need to add the property dm-pre-reloc to the soc node,
we can delete it from bcm283x-uboot.dtsi

Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
d2086d6633 pinctrl: bcm283x: Add compatible for RPi4
The Raspberry Pi 4 upstream kernel device tree instroduces
a new compatible for the pinctroller. Add this to the driver
so that we can boot with the upstream kernel DT.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Tom Rini
9a0cbae22a Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean vid/pid in Kconfig and add fastboot for rk3399
- add 'u-boot, spl-fifo-mode' for mmc
- Use FIT generator for rk3229 optee and rk3368 ATF
- fan53555: add support for Silergy SYR82X and SYR83X
2019-11-23 20:50:11 -05:00
Tom Rini
c8f2fe4e67 Merge branch '2019-11-23-master-imports'
- More travis job splits
- Assorted build clean-ups
- Correct optimization flags for some ARMv6 platforms
2019-11-23 20:48:47 -05:00
Heinrich Schuchardt
16540d07fd arm: fix -march for ARM11
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html

ARM11 is an armv6 implementation. So change the architecture flag for the
compiler to armv6 for ARM11.

Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-11-23 14:53:48 -05:00
Tom Rini
70f6813985 buildman: Fix problem with non-existent output directories
Now that we have buildman telling genboards.cfg to use an output
directory we need to ensure that it exists.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Fixes: bc750bca12 ("tools: buildman: Honor output directory when generating boards.cfg")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-23 14:53:48 -05:00
Bartosz Golaszewski
163b7641f8 scripts: dtc: ignore files generated generated by python
Add __pycache__ to ignored files and extend the rule for _libfdt to also
include generated shared objects (e.g. _libfdt.cpython-37m-x86_64-linux-gnu.so).

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-11-23 14:53:48 -05:00
Tom Rini
02b5670e65 moveconfig.py: Fix more Python3 UTF issues
With the move to using Python 3 for real, we encounter two different
issues.  First, the file include/video_font_data.h includes at least one
UTF-16 character.  Given that it does not include any CONFIG symbols it
is easiest to just ignore this file.  Next, we encounter similar
problems with some dts/dtsi files that come from Linux.  In this case
it's easiest to simply ignore all dts/dtsi files as there will not be
CONFIG symbols for us to migrate in them.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-23 14:53:48 -05:00
Heiko Stuebner
8019d32c47 rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evb
As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.

The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.

There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-11-23 23:41:44 +08:00
Heiko Stuebner
c8dd0e42d7 rockchip: dwmmc: add handling for u-boot, spl-fifo-mode
Rockchips dwmmc controllers can't do dma to non-ddr addresses,
like for example the soc-internal sram but during boot parts of
TrustedFirmware need to be placed there from the read FIT image.

So add handling for a u-boot,spl-fifo-mode to not put the mmc
controllers into fifo mode for all time.

The regular fifo-mode property still takes precedent and only
if not set do we check for the spl-specific property.

Suggested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-11-23 23:41:44 +08:00
Jagan Teki
d4fba131bb rock960: Enable USB Gadget
Enable DWC3 core, gadget for rock960 board.

This would help to use fastboot by default.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 23:41:44 +08:00
Jagan Teki
c618bb0042 rockchip: Setup dwc3_device (for non-dm gadgets)
Setup dwc3_device structure for non-dm gadgets, which is used
in rk3399 platforms.

dwc3_device would have basic regbase, dr_mode, high speed
and 16-bit UTMI+ etc.

Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix to use CONFIG_USB_DWC3_GADGET instead of CONFIG_USB_DWC3)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 23:41:44 +08:00
James Byrne
66b3ccc8f7 tools: checkpatch: Restore 'debug' and 'printf' to logFunctions list
The 'debug' and 'printf' functions were previously added to the list of
logFunctions in commit 0cab42110d ("checkpatch.pl: Add 'debug' to
the list of logFunctions") and commit 397bfd4642 ("checkpatch.pl:
Add 'printf' to logFunctions") but these additions were lost when newer
versions of checkpatch were pulled in from the upstream Linux
kernel version.

This restores them so that you don't end up in a situation where
checkpatch will give a warning for "quoted string split across lines"
which you cannot fix without getting a warning for "line over 80
characters" instead.

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
2019-11-23 10:28:56 -05:00
Heiko Schocher
af77162504 travis: rework NXP layerscape jobs
remove from NXP arm32 all layerscape boards and
build them instead in already existing layerscape
jobs (which now not only build aarch64 boards)

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-11-23 10:28:56 -05:00
Heiko Schocher
56d35f2ed4 travis: move orangepi to vendor job
move orangepi builds into a new job, and exclude
orangepi builds from sunxi and rockchip jobs.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-23 10:28:56 -05:00
Tom Rini
601c2879f8 Pull request for UEFI sub-system for efi-2020-01-rc4 (2)
Use CONFIG_EFI_LOADER=n for ARM11 except for the Raspberry Pi and the
 Raspberry Pi Zero.
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Merge tag 'efi-2020-01-rc4-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-01-rc4 (2)

Use CONFIG_EFI_LOADER=n for ARM11 except for the Raspberry Pi and the
Raspberry Pi Zero.
2019-11-23 10:20:18 -05:00
Jagan Teki
3d3b83a573 gadget: rockchip: Add rk3399 USB_GADGET_PRODUCT_NUM
Add 0x330c for rk3399 gadget product number.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00