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2 commits

Author SHA1 Message Date
Mark Jackson
296de3bbec Initialise correct GPMC WAITx irq for AM33xx 
Currently WAIT0 irq is reset and then WAIT1 irq is enabled.
Fix it such that WAIT0 irq is enabled instead.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
 2013-03-22 10:57:00 -04:00
Ilya Yanok
8eb16b7f73 am33xx: NAND support 
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
 2012-12-10 08:54:01 -07:00