Commit graph

64703 commits

Author SHA1 Message Date
Weijie Gao
814a8916a9 mips: add an option to enable u_boot_list section for SPL loaders in u-boot-spl.lds
u_boot_list is not only used by DM, but also by some SPL image load methods
such as spl_nor.c.

This patch adds an option CONFIG_SPL_LOADER_SUPPORT in conjunction with
CONFIG_SPL_DM surrounding the u_boot_list section to make sure SPL image
loaders can be correctly built into u-boot SPL without DM enabled.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
e9511193fa mips: enable support for appending dtb to spl binary
If CONFIG_SPL_OF_CONTROL is enabled for SPL and CONFIG_OF_SEPARATE is also
enabled, the dtb will be appended to the u-boot-spl.bin.

When calling dm_init_and_scan() in SPL, fdtdec_setup() will try to locate
dtb at the end of u-boot-spl.bin, by referencing to _image_binary_end.

However _image_binary_end is currently missing in u-boot-spl.lds.
This patch adds _image_binary_end to u-boot-spl.lds to make sure linking
u-boot-spl will not fail.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
6e9281b559 mips: start.S: avoid overwriting outside gd when clearing global data in stack
When setting up initial stack, global data will also be put in the stack,
and being cleared.

The assembler instructions for clearing gd is as follows:

	move	t0, k0
1:
	PTR_S	zero, 0(t0)
	blt	t0, t1, 1b
	 PTR_ADDIU t0, PTRSIZE

t0 is the start address of gd, t1 is the end address of gd (t0 + GD_SIZE).

[PTR_ADDIU t0, PTRSIZE] is in the delay slot of [blt t0, t1, 1b], so it
will be executed before the branch operation.

However the comparison for the BLT instruction is done before executing the
delay slot. This means when the last word just before k1 is cleared, the
loop will continue to run once. This will clear an extra word at k1, which
is outside the global data.

Global data is placed at the top of the stack. If the initial stack is a
SRAM or locked cache, the area outside them may be inaccessible. A write
operation performed in this area may cause an exception.

To solve this, [PTR_ADDIU t0, PTRSIZE] should be placed before the BLT
instruction.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
79765201ca mips: mtmips: add predefined i-cache/d-cache size and linesize
Both mt7620 and mt7628 has the same cache configuration. There is no need
to use CONFIG_SYS_CACHE_SIZE_AUTO to probe it at runtime.

Add them into Kconfig to reduce some code size.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
ce7e197ea5 configs: enable CONFIG_RESTORE_EXCEPTION_VECTOR_BASE for all mtmips boards
This patch enables CONFIG_RESTORE_EXCEPTION_VECTOR_BASE for all mtmips
boards.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
71059736b8 mips: add support to restore exception vector base before booting linux
In U-Boot the exception vector base will be moved to top of memory, to be
used to display register dump when exception occurs.

But some old linux kernel does not honor the base set in CP0_EBASE. A
modified exception vector base will cause kernel crash.

This patch adds an option to enable reset exception vector base to its
previous value, or a user configured value before booting linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Álvaro Fernández Rojas
56ed625ba2 bmips: allow disabling usb support
Currently, if usb is disabled the following error is produced:
  CC      drivers/usb/host/ohci-hcd.o
drivers/usb/host/ohci-hcd.c: In function ‘usb_lowlevel_init’:
drivers/usb/host/ohci-hcd.c:2057:35: error: ‘CONFIG_SYS_USB_OHCI_REGS_BASE’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_MONITOR_BASE’?
  gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
                                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                   CONFIG_SYS_MONITOR_BASE
drivers/usb/host/ohci-hcd.c:2057:35: note: each undeclared identifier is reported only once for each function it appears in
drivers/usb/host/ohci-hcd.c:2061:20: error: ‘CONFIG_SYS_USB_OHCI_SLOT_NAME’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS’?
  gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                    CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2020-04-27 20:29:33 +02:00
Álvaro Fernández Rojas
b9ec102bc4 nand: brcmnand: return without disabling clock
Linux Broadcom NAND driver only disabled clock if no childs are initialized.
This section of the code seems to have been accidentally dropped when it was
imported in U-Boot.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-04-27 20:29:33 +02:00
Tom Rini
d16d37bcd4 - simple panel 'nv140fhmn49' compatible
- rockchip eDP and LVDS drivers build fix
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Merge tag 'video-for-v2020.07-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- simple panel 'nv140fhmn49' compatible
- rockchip eDP and LVDS drivers build fix
2020-04-27 09:41:51 -04:00
Patrick van Gelder
27d706937a ARM: zynq: Fix invalid check on NAND_CMD_NONE.
The end_cmd field in the variables cmd_phase_addr and data_phase_addr
contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This
should be 0x00.

This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8).
end_cmd will be promoted by the int value -1 and therefore is not equal
to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int
promotion.

Signed-off-by: Patrick van Gelder <patrick.vangelder@nl.bosch.com>
Reviewed-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
Michal Simek
19d1304505 xilinx: Make Xilinx custom distro boot commands more verbose
Extend description of Xilinx custom boot commands to make clear what runs
and what failed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
T Karthik Reddy
7a3e239e90 ARM: zynq: Change SYS_MALLOC_LEN in zynq_cse_nand_defconfig
nand_scan_tail() function allocates memory dynamically for
struct nand_buffers which needs ~21kbytes of memory. But the
memory alloted with CONFIG_SYS_MALLOC_LEN is 4k which is insufficient.
Increase CONFIG_SYS_MALLOC_LEN to 32Kbytes from which struct
nand_buffers uses ~21kbytes & remaining memory is used for other.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
T Karthik Reddy
e86dce1c0c ARM: zynq: Add nand controller node in zynq-ces-nand dt
Add memory-controller@e000e000 node in zynq-ces-nand.dts as
zynq_nand driver utilizes flash@e1000000 node. Without this
dt node mini nand u-boot does not probe.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
Michal Simek
14c0fbbc94 arm64: zynqmp: Fix irps5401 device nodes
- Do not use irps54012 as device node which is not correct.
- Fix addresses of irps5401/u180 on zcu104 revisions.
- Remove clock-cells property. It is PMIC without any clock output.
- Define irps5401 nodes in zynqmp-e-a2197

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
Eugeniy Paltsev
73b3c23e48 ARC: AXS10x: cleanup kconfig
As we've dropped NAND support for AXS101 and AXS103
see commit 4f5e552d95 ("ARC: AXS10x: drop NAND support")
we don't need bounce buffer anymore.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 15:04:42 +03:00
Michal Simek
51f6c52e6b xilinx: Move bootmode detection to separate function
Create special function for reading bootmode on Versal and ZynqMP.
Zynq is using specific function (without mask) already.
Future patches will be calling this function from different location too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:57:18 +02:00
Michal Simek
a29511eeca xilinx: Move initrd_high setup to common location
Moving to common location initrd_high is also setup for Zynq which hasn't
done in run time code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:57:18 +02:00
Saeed Nowshadi
783814288b arm64: zynqmp: Add label to GPIO lines for boot mode and POR
Add label to GPIO lines controlling boot mode and POR EMIO pins so System
Controller can assert those lines on Versal.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:57:18 +02:00
T Karthik Reddy
7eab624baf clk: versal: Fix watchdog clock issue
Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt
driver. Skip reading clock rate for the mux based clocks with
parent clock id is zero.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
2020-04-27 13:57:17 +02:00
Michal Simek
dec206a09b xilinx: zynqmp: Fix MIO 18 configuration on zcu104 revC
Without this change QSPI is not detected on zcu104 revC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:57:17 +02:00
Michal Simek
80fdef12b2 xilinx: Introduce board_late_init_xilinx()
This function should keep common shared late configurations for Xilinx
SoCs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:57:17 +02:00
Michal Simek
b72f450527 ARM: zynq: Setup stack size via Kconfig
Stack size has been introduced by commit a69814c815 ("arm64: zynqmp:
Set initrd_high to as high as possible") and commit 085201c246 ("arm64:
versal: Set initrd_high to as high as possible")
to support setting up initrd_high as high as possible.
The same change should happen for Zynq because the code is moved to xilinx
common location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:53:13 +02:00
Michal Simek
26ee8fc369 xilinx: Enable MTD and UBIFS for zynq and zynqmp
Both of them have nand controller that's why it is good to enable it
because these configurations are also covered by testing.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:53:13 +02:00
Benedikt Grassl
942b5fc032 mmc: zynq: parse dt when probing
Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes
is not evaluated. This results in the bus width staying at its default
value (4 bit in HS200 mode).
Fix this by calling mmc_of_parse. This function also checks for the
"no-1-8-v" and "max-frequency" entries. Remove the handling of those
nodes from this driver.

Signed-off-by: Benedikt Grassl <Benedikt.Grassl@rohde-schwarz.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:53:13 +02:00
Eugeniy Paltsev
25998aed4d ARC: HSDK-4xD: make init status resistant to U-boot reloading
Use register intstead of static variable to store HSDK init status as
we want to avoid the situation when we reload U-boot via MDB after
previous init is done but HW reset (board reset) isn't done. So
let's store the init status in unused register - CREG_CPU_0_ENTRY
so status will survive after U-boot is reloaded via MDB.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:27 +03:00
Eugeniy Paltsev
3ad73b75a7 ARC: HSDK-4xD: use separate config file
HSDK-4xD has quite different environment so let's split
HSDK and HSDK-4xD configs file.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:27 +03:00
Eugeniy Paltsev
32ac4ee6fd ARC: HSDK-4xD: tweak memory map
For HSDK-4xD we do additional AXI bridge tweaking while doing
hsdk_init command:
 - we shrink IOC region.
 - we configure ARC HS CORE SLV1 aperture depending on
   haps_apb_location environment variable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:27 +03:00
Eugeniy Paltsev
6917a9dbaf ARC: HSDK-4xD: add CSM configuration support
Add support for CSM enable/disable and CSM relocation via
hsdk_init command. We allow to relocate CSM to the beginning of
any aperture even if HW support finer granularity.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:27 +03:00
Eugeniy Paltsev
1d897d1a22 ARC: HSDK-4xD: add support for SLC enable/disable
Add support for SLC enable/disable via hsdk_init command.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
d4ee5c39ba ARC: HSDK-4xD: print timer clock value
Print timer clock value in hsdk_clock print_all command.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
da34c6b7dd ARC: HSDK-4xD: drop additional GPU clock info
HSDK-4xD has other GPU type so it consumes only GPU core clock.
Even we have additional GPU clock dividers they are not routed
to anything. So drop information about those additional clocks
in hsdk_clock print_all command.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
b84aa4cc1d ARC: HSDK-4xD: print info about HDMI clocks
HSDK-4xD has HDMI working so let's print info about HDMI clocks.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
e31fdd8170 ARC: HSDK-4xD: fix headerize script for HSDK-4xD compatibility
ARC HS CPU in HSDK-4xD has ARC ID = 0x54, so fix headerize script
accordingly.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
4b4da7ff61 ARC: HSDK-4xD: use active low polarity of cpu_start pulse
Add quirk for HSDK-4xD - due to HW issues HSDK can use any pulse
polarity but HSDK-4xD require active low polarity of cpu_start pulse.

So use low polarity of cpu_start pulse for both board.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
28db0d693f ARC: HSDK: split HSDK and HSDK-4xD DTS
Split HSDK and HSDK-4xD device tree files so they can have
different model names.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
f0f84efe45 ARC: HSDK-4xD: add initial board support
Add initial HSDK-4xD board support.
The ARC HS4x/HS4xD Development Kit includes a multicore ARC HS4xD-based
chip that integrates a wide range of interfaces including Ethernet,
HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and
GPIO, as well as a Think Silicon GPU.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:25 +03:00
Eugeniy Paltsev
1dfb2ec0d7 ARC: HSDK: CGU: add support for timer clock
Add support for additional timer clock which belongs to tunnel
domain.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:25 +03:00
Eugeniy Paltsev
61c151693b ARC: ARCv2: handle DSP presence in HW
In case of DSP extension presence in HW some instructions
(related to integer multiply, multiply-accumulate, and divide
operation) executes on this DSP execution unit. So their
execution will depend on dsp configuration register (DSP_CTRL)
As we want these instructions to execute the same way regardless
of DSP presence we need to set DSP_CTRL properly.

NOTE:
we do the same adjustments in Linux kernel, see in kernel tree:
commit 4827d0cf744e ("ARC: handle DSP presence in HW")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:25 +03:00
Ley Foon Tan
b9d1671829 arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.

Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-27 09:14:52 +02:00
Ley Foon Tan
c336d7431c configs: socfpga: arria10: Enable USB support
Enable configs to support USB in Arria 10.

CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-27 09:14:52 +02:00
Peter Robinson
ea16637525 video: simple_panel: add boe,nv140fhmn49 display
add "boe,nv140fhmn49" display to compatible node.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
2020-04-26 23:04:49 +02:00
Peter Robinson
973e31fd47 drivers: video: rockchip: fix building eDP and LVDS drivers
The rk_edp.c and rk_lvds.c files reference rk_setreg which is declared in
hardware.h so include it so the drivers build. Adjust rk_lvds.c so
includes are in alphabetical order while updating.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
2020-04-26 22:58:50 +02:00
Heinrich Schuchardt
c1f39edc62 log: remove useless cast
There is no need to cast from (void *) before assigning to a pointer.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
b4fa94959d patman: Tidy up sys.path changes
Now that we are using absolute paths we can remove some of the sys.path
mangling that appears in the tools.

We only need to add the path to 'tools/' so that everything can find
modules relative to that directory.

The special paths for finding pylibfdt remain.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
bf776679a7 patman: Move to absolute imports
At present patman sets the python path on startup so that it can access
the libraries it needs. If we convert to use absolute imports this is not
necessary.

Move patman to use absolute imports. This requires changes in tools which
use the patman libraries (which is most of them).

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
16287933a8 binman: Move to absolute imports
At present binman sets the python path on startup so that it can access
the libraries it needs. If we convert to use absolute imports this is not
necessary.

Move binman to use absolute imports. This enables removable of the path
adjusting in Entry also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
0ede00fdaf buildman: Move to absolute imports
At present buildman sets the python path on startup so that it can access
the libraries it needs. If we convert to use absolute imports this is not
necessary.

Move buildman to use absolute imports. Also adjust moveconfig.py too since
it uses some buildman modules and cannot work without this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
ce0dc2edfc patman: Move test running/reporting to test_util
This code is useful in other tools. Move it into a common file so it can
be shared.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
428e773011 patman: Drop the python2 code in test coverage
We don't need to run test coverage with Python 2 now. Drop the
special-case code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00
Simon Glass
76160801b0 Add a 'make tcheck' option to test tools
Running all the unit tests takes a while and is not useful when you are
just modifying the tools. Add an option to run only the tools tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-26 14:25:21 -06:00