Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
div_mask is different for GENERIC and USB pll, so set it according.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Since some driver requires this function add it as an empty stub
when DCACHE is OFF.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
At the moment entry_point is set to image_get_load(header) that sets it
to "load address" instead of "entry point", assuming entry_point is
equal to load_addr, but it's not true. Then load_addr is set to
"entry_point - header_size", but this is wrong too since load_addr is
not an entry point.
So use image_get_ep() for entry_point assignment and image_get_load()
for load_addr assignment.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
IPG clock description is missing for I2C0 and I2C2 busses,
add it. Otherwise we see -ENODATA error when trying to get
I2C clock for these busses.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
imx6ul-14x14-evk does not have a GPIO dedicated for reading the card
detect pin on the eSDHC2 port. In such cases the "broken-cd" property
must be passed, otherwise the card cannot be detected.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
When no GPIO is used to read the card detect status the following
error is seen:
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by handling the "broken-cd" property in the same way
that drivers/mmc/sdhci.c does, which considers that the SD card
is present when the "broken-cd" property is passed.
Tested on a imx6ul-evk board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
For DM_ETH support , it's require to disable this config.
When this config is enable, This generate a error with spl in linker script
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Currently the following SPL hang is observed:
U-Boot SPL 2020.01-rc5-00079-g797eee36a1 (Jan 06 2020 - 11:24:09 -0300)
Trying to boot from MMC1
Card did not respond to voltage select!
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix it by moving the eSDHC2 initialization to SPL.
While at it, since this board uses DM_MMC all the esdhc board
code can be removed to make the code simpler.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Only the wandboard revD1 boards have PMIC, so when running on a wandboard
of different revision the following error is always shown on every boot:
pmic_get() ret -19
Instead of printing this error message, move it to debug level instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Some i.MX8QXP MEK boards do not have MAC address stored
and hang during eth driver probe:
Error: ethernet@5b040000 address not set.
(Board hangs)
To fix this problem select CONFIG_NET_RANDOM_ETHADDR so that
a valid MAC address can be used in such case.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
All Tegra chips except Tegra186 have a tegraNNN-u-boot.dtsi. Duplicate
Tegra210's copy of this file for Tegra186. This ensures that a /binman node
exists in U-Boot's control DT. Subsequent to 3c10dc95bd ("binman: Add a
library to access binman entries") this appears to be required. I haven't
really investigated why all this is necessary or how it works, but simply
observed the boot failure listed below, bisected it, noticed the
inconsistency in DT files, and found that fixing it resolved the boot
issue.
U-Boot 2020.01-rc4-00256-g3c10dc95bdd0 (Jan 07 2020 - 10:25:00 -0700)
SoC: tegra186
Model: NVIDIA P2771-0000-500
Board: NVIDIA P2771-0000
DRAM: 7.8 GiB
initcall sequence 00000000fffb7858 failed at call 00000000800955a8 (err=-22)
### ERROR ### Please RESET the board ###
Fixes: 3c10dc95bd ("binman: Add a library to access binman entries")
Fixes: f2faffecb0 ("binman: tegra: Convert to use binman")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Qemu v4.2.0 maps bootmode registers to address space which was the reason
why board_late_init() was disabled and accesses were failing.
With new Qemu board_late_init() can be called without any issue.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Most of the legacy "gpio-key,wakeup" boolean property is already
replaced with "wakeup-source". However few occurrences of old property
has popped up again, probably from the remnants in downstream trees.
This patch replaces the legacy properties with the unified
"wakeup-source" property introduced by:
"Input: gpio_keys - switch to using generic device properties"
(sha1: 700a38b27eefc582099fdf69effacfad0ad738a4)
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Somewhere along recent changes to power control of the wl1831, power-on
became very unreliable on the Ultra96, failing like this:
wl1271_sdio: probe of mmc2:0001:1 failed with error -16
wl1271_sdio: probe of mmc2:0001:2 failed with error -16
After playing with some dt parameters and comparing to other users of
this chip, it turned out we need some power-on delay to make things
stable again. In contrast to those other users which define 200 ms,
Ultra96 is already happy with 10 ms.
Fixes: 5869ba0653b9 ("arm64: zynqmp: Add support for Xilinx zcu100-revC")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
s/_/-/ for node names.
It fixes warnings like this:
... Warning (node_name_chars_strict): /cpu_opp_table:
Character '_' not recommended in node name ...
Issues reported by make dtbs W=12
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.
This fixes warnings generated by the DT schema.
Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
zcu102-revB/up are not removing phy from revA properly because of incorrect
name.
Fixes: 2975a42b42 ("arm64: zynqmp: Use ethernet-phy as node name for ethernet phys")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zcu1285 is the same as zcu1275 but it is using Avnet FMC
http://www.ultrazed.org/product/network-fmc-module
Unfortunately not everything is connected now that's why this is only
describing system which Xilinx is using.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Removed no-1-8-v property from zynqmp sdhci devicetree nodes to
allow UHS-I capable SD cards to work in SD3.0 UHS modes.
Boards that does not have level shifter for SD, does not support 1.8v.
so no-1-8-v property to sdhci dt nodes should be present in zcu102 Rev-A,B,
zcu104 Rev-A,C, zcu100, zcu1275 Rev-B boards.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver.
It is just binding its subnode zynqmp-clk.
As a result one extra node is showing up in dm tree.
This is not required, it is anyway bound from it's own zynqmp-clk driver.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Corrected the type of eeprom in device tree for zcu216 boards according
to schematic.
Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix shunt resistor value for ina226 vccint_ams and vccint_io_bram_ps.
2mOhm shunt was only in early board revision schematics but never got to
real revA board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Decrease amount of the similar defconfigs and use generic one instead.
The change was declared by commit 4b37c13dc3
("arm64: zynqmp: Introduce virtual defconfig") and this patch removes
configs for the most of the boards.
Utra96/zcu100/zcu102/zcu102 and ZynqMP based System controllers *a2197*.
have been also boot tested to make sure that funcionality
remains the same.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
These options are taken from zcu102/104 platforms. Also use OF_SEPARATE
instead of OF_BOARD. Maybe at some point this option will be taken back but
as of now board detection is not ready.
export DEVICE_TREE="zynqmp-zcu102-revA"
make xilinx_zynqmp_virt_defconfig
make -j
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which
includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for
quite a long time but with using out of tree solution. The patch is filling
this gap.
Tested on zcu102, zcu104 and zcu100/Ultra96.
zcu100/Ultra96 v2.2 ATF build by:
make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Extend test suite to cover also automatic octal/hex converstions which
haven't been implemented in past.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
All drivers should be converted to DM already that's why these hardcoded
base addresses are not needed anymore.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove hardcoded base addresses of smc controller and nand controller.
Get those addresses from dt and replace wherever they are used.
Remove smc and nand base address from header file too.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
