This set of ifdefs is used in a number of places. Move its definition
somewhere common so it doesn't have to be repeated.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
All Tegra devices will need CONFIG_BOUNCE_BUFFER. Move it to
tegra-common.h to ensure it's always set.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested on my Cardhu-A04 tablet, eMMC and SD-Card work fine, can load
a kernel off of an SD card OK, card detect works, and the env is now
stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tegra30 SD/MMC controller differs enough from Tegra20 that it
needs its own entry in the compat_names/compat_id tables and in
the Tegra MMC driver.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tegra30 requires the SD Bus Voltage & Power bits be set in the SD
Power Control register. Tegra20 works w/o them set, but do it anyway
for those SoCs as it's part of the SD spec. Also call a common
board pad init routine (pad_init_mmc) in mmc_reset(), used by
Tegra30 only for now.
Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a
new compatible entry is used in the fdt compat_names/id tables.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
T30 requires specific SDMMC pad programming, and bus power-rail bringup.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Removed SDMMC base addresses from tegra.h since they're no longer used.
Added additional vendor-specific SD/MMC registers and bus power defines.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().
Currently, only SDIO1CFG is changed as per the TRM to work with
the SD-card slot on Cardhu.
Thanks to StephenW for the suggestion/original idea.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Use the latest tables & code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
This was an older debug/developmental file that got added
accidentally. Not needed/used in any Cardhu build.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
A Tegra114 HW bug prevents the main CPU vector from being modified under
certain circumstances. Tegra114 A01P and later with a patched boot ROM
set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing
an arbitrary jump instruction at that location, in order to redirect to
the desired reset vector location. Modify Tegra114's start_cpu() to make
use of this feature. This allows CPUs with the patched boot ROM to boot.
Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.
Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Linux dts files were used for those boards that didn't already
have sdhci info populated. Tamonten has their own dtsi file with
common sdhci nodes (sourced from Linux).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
dts Makefile has the arch & board include paths added to DTS_CPPFLAGS.
This allows the use of '#include "xyz"' in the dts/dtsi file which
helps the C preprocessor find common dtsi include files.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested all 5 'buses', i2c probe enumerates device addresses on bus
0, 1 and 2.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.
Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives).
This is needed so that the SDIO slot power can be brought up for
the MMC driver, so it has to precede those commits.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
The ehci_hcd entry points were just calling into the Tegra USB
functions. Now that they are in the same file we can just move over the
implementation.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This moves the Tegra USB implementation into the drivers/usb/host
directory. Note that this merges the old
/arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code
changes, just moving stuff around.
v2: While at it also move some defines and the usb.h header file to make
usb driver usable for Tegra30.
NOTE: A lot more work is required to properly init the PHYs and PLL_U on
Tegra30, this is just to make porting easier and it does no harm here.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Remove unneeded headers, function prototype and stale comment, that
doesn't match the actual codebase anymore.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no need to init a USB controller before the upper layers indicate
that they are actually going to use it.
board_usb_init now only parses the device tree and sets up the common pll.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Just a dead parameter, never actually used.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no need to pass around all those parameters. The init functions
are able to easily extract all the needed setup info on their own.
This allows to move out the controller init into ehci_hcd_init later
on, without having to save away global state for later use and thus
bloating the file global state.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Both Tegra20 and Tegra30 have a max of 3 USB controllers.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such,
some CPU errata exist, and must be worked around.
These must be worked around in the bootloader, since in general, the
kernel (especially a multi-platform kernel) needs to support being
launched in non-secure mode (normal world), and hence may not be able
to write to the CP15 register to enable these workarounds.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.
This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.
Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.
Conflicts:
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/vpac270/u-boot-spl.lds
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Turn __bss_start and __bss_end__ from linker-generated
to compiler-generated symbols, causing relocations for
these symbols to change type, from R_ARM_ABS32 to
R_ARM_RELATIVE.
This should have no functional impact, as it affects
references to __bss_start and __bss_end__ only before
relocation, and no such references are done.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.
This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.
Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.
This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
This patch corrects the following issues
1) Write the correct M/T Stop value to I2CSTAT after i2c write.
According to the spec, after finish the data transmission, we should
write a M/T Stop (I2C_MODE_MT | I2C_TXRX_ENA) to I2CSTAT instead of
a M/R Stop (I2C_MODE_MR | I2C_TXRX_ENA).
2) Not split the write to I2CSTAT into 2 steps in i2c read.
According to the spec, we should write the combined M/R Start value to
I2CSTAT after setting the slave address to I2CDS
3) Fix the mistake of making an equality check to an assignment.
In the case of I2C write with the zero-length address, while tranfering the
data, it should be an equality check (==) instead of an assignment (=).
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
This revomes the code under #if 0 in the s3c24x0_i2c driver.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Because the code that handles bootdelay is compiled in conditionally
based on the default value, you are restricted in the default,
regardless of what you want the runtime options to be.
Change the source to always check if any default is given so that other
values can be selected and used at runtime.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
The "env ask" traditionally uses a somewhat awkward syntax:
env ask name [message ...] [size]
So far, when a mesage was given, you always also had to enter a size.
If you forgot to do that, the command would terminate without any
indication of the problem.
To avoid incompatible changes of the interface, we now check the last
argument if it can be converted into a decimal number. If this is the
case, we assume it is a size; otherwise we treat it as part of the
message.
Also, add a space after the message fore easier reading,
and clean up help mesage.
Signed-off-by: Wolfgang Denk <wd@denx.de>
When using the partial read feature of fatwrite the buffer we read into
can become unaligned not just due to initial location but the size of
our partial reads as well. Make this clear in the help text.
Signed-off-by: Tom Rini <trini@ti.com>
As the CPU name is not configurable, using CPU string directly
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
