Commit graph

9265 commits

Author SHA1 Message Date
Tom Rini
aadd3360e6 ARM: keystone2: Split monitor code / command code
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case, we split the code for
supporting the monitor out from the code for loading it.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16 15:03:15 -04:00
Nishanth Menon
3eb80d10c7 ARM: DRA7: DDR: Enable SR in Power Management Control
If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 21:30:19 -04:00
Alexander Graf
cc4a474873 arm: Allow EFI payload code to take exceptions
There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, r9 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 21:30:13 -04:00
Alexander Graf
649829157e arm64: Allow EFI payload code to take exceptions
There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, x18 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 21:30:11 -04:00
Alexander Graf
4c2cc7c4e9 arm64: Allow exceptions to return
Our current arm64 exception handlers all panic and never return to the
exception triggering code.

But if any handler wanted to continue execution after fixups, it would
need help from the exception handling code to restore all registers.

This patch implements that help. With this code, exception handlers on
aarch64 can successfully return to the place the exception happened (or
somewhere else if they modify elr).

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 21:30:10 -04:00
Alexander Graf
50149ea37a efi_loader: Add runtime services
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.

This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.

We could maybe in the future map U-boot environment variables to EFI variables
here.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-03-15 18:03:10 -04:00
Alexander Graf
19503c3117 arm64: Only allow dcache disabled in SPL builds
Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:11 -04:00
Alexander Graf
7985cdf74b arm64: Remove non-full-va map code
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:10 -04:00
Alexander Graf
b30291a3b2 tegra: Replace home grown mmu code with generic table approach
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:04 -04:00
Alexander Graf
96519f31cb zymqmp: Replace home grown mmu code with generic table approach
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:03 -04:00
Alexander Graf
d473f0c621 thunderx: Move mmu table into board file
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:02 -04:00
Alexander Graf
5e2ec773bb arm64: Make full va map code more dynamic
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.

So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.

With all this in place, there is very little reason to create your
own page tables in board specific files.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:01 -04:00
Alexander Graf
9bb367a590 arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:00 -04:00
Alexander Graf
0691484ac1 thunderx: Calculate TCR dynamically
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:12:59 -04:00
Paul Kocialkowski
69847dd8f0 omap4: Check warm reset for reboot mode validity
Since the SAR registers are filled with garbage on cold reset, this checks for a
warm reset to assert the validity of reboot mode.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:54 -04:00
Paul Kocialkowski
faec3f9841 omap4: Reboot mode support
Reboot mode is written to SAR memory before reboot in the form of a string.

This mechanism is supported on OMAP4 by various TI kernels.

It is up to each board to make use of this mechanism or not.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:53 -04:00
Paul Kocialkowski
6e495a453f omap4: Properly enable USB PHY clocks
This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:50 -04:00
Paul Kocialkowski
5e56b0a80e omap-common: clocks-common: Setup USB DPLL when MUSB is in use
On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY
to work properly. The internal PHY is used by default with the MUSB USB OTG
controller.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:49 -04:00
Paul Kocialkowski
ae51b5709e Amazon Kindle Fire (first generation) codename kc1 support
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.

It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:48 -04:00
Paul Kocialkowski
14689ad79e omap4: Move i2c clocks enable to enable_basic_clocks
I2C is often enabled withing the U-Boot SPL, thus those clocks are required to
be enabled early (especially when the bootrom doesn't enable them for us).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:47 -04:00
Paul Kocialkowski
437086b1da omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespace
This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin
enable_basic_uboot_clocks. Also, a doubled whitespace is removed.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:46 -04:00
Paul Kocialkowski
3832e54673 omap-common: Remove deprecated arch_cpu_init code
save_omap_boot_params is called from spl_board_init in the SPL context. Thus,
there is no reason to duplicate that call on arch_cpu_init.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:46 -04:00
Paul Kocialkowski
3ef56e61c8 omap-common: Rename set_muxconf_regs_essential to set_muxconf_regs
There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:12:06 -04:00
Paul Kocialkowski
ed5ddebe96 omap4: Export jedec sdram timings
Individual boards might provide their own emif_get_device_timings function and
use the jedec timings in their own way, hence those have to be exported.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:32 -04:00
Paul Kocialkowski
96703acd0a omap4: Export elpidia sdram timings
Individual boards might provide their own emif_get_device_timings function and
use the elpidia timings in their own way, hence those have to be exported.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:31 -04:00
Paul Kocialkowski
7cb998ba85 omap4: Export elpidia sdram device details
Individual boards might provide their own emif_get_device_details function and
use elpidia device details in their own way, hence those have to be exported.

This also wraps existing definitions with the proper ifdef logic.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-03-15 15:11:30 -04:00
Paul Kocialkowski
90ca5dfec4 omap3: Use a define for reboot reason offset
This introduces a define for the offset to the reboot reason, rather than
hardcoding it.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 15:10:48 -04:00
Paul Kocialkowski
c5412b084b omap3: String-based reboot mode handling
This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 15:10:47 -04:00
Tom Rini
4d339a9e8a Merge branch 'master' of git://git.denx.de/u-boot-video 2016-03-15 08:01:17 -04:00
Tom Rini
88033d737d Merge git://git.denx.de/u-boot-dm 2016-03-14 19:21:44 -04:00
Masahiro Yamada
0ea6cc1253 arm64: define _image_binary_end to fix SPL_OF_CONTROL
To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be
defined in the linker script.

 LD      spl/u-boot-spl
lib/built-in.o: In function `fdtdec_setup':
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

Note:
CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:52 -04:00
Lokesh Vutla
a7638833b3 ARM: DRA7: Move emif settings to board specific files
The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.

Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-14 19:18:50 -04:00
Lokesh Vutla
25afe55de5 ARM: DRA7: Enable EEPROM support
Enable EEPROM support for DRA74-evm.

Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-14 19:18:50 -04:00
Adam Ford
2f6ed3b89a ARM: Various: Future-proof serial platdata
A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.

Tested on the Logic PD Torpedo + Wireless.

I only changed a handful of devices that used the same syntax as the Logic
board.  Appologies if I missed one or stepped on toes.  Thanks to Derald Woods
and Alexander Graf.

Signed-off-by: Adam Ford <aford173@gmail.com>

V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c

V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c

V4: Fix subject heading

V3: Remove  reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.

V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-14 19:18:48 -04:00
Lokesh Vutla
e850ed82bc ARM: OMAP4+: Allow arch specfic code to use early DM
Early system initialization is being done before initf_dm is being called
in U-Boot. Then system will fail to boot if any of the DM enabled driver
is being called in this system initialization code. So, rearrange the
code a bit so that DM enabled drivers can be called during early system
initialization.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:48 -04:00
Lokesh Vutla
29c20ba235 ARM: DRA7: emif: Enable interleaving for higher address space
Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Lokesh Vutla
e3ce3aa103 ARM: DRA7: emif: Check for enable bits before updating leveling output
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:47 -04:00
Lokesh Vutla
4571c519b4 ARM: DRA7: emif: Fix DDR init sequence during warm reset
Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:46 -04:00
Lokesh Vutla
de09547478 ARM: DRA7: emif: Fix updating of refresh ctrl shadow
On DRA7, refresh ctrl shadow should be updated with
the final value.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:46 -04:00
Vitaly Andrianov
8efc243741 ARM: keystone2: use detected ddr3a size
Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.

This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.

For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:45 -04:00
Vitaly Andrianov
d9a76e77c8 ARM: keystone2: use SPD info to configure K2HK and K2E DDR3
This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.

The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:44 -04:00
Lokesh Vutla
ef76ebb1ef ARM: keystone2: K2G: Add support for different arm/device speeds
The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:44 -04:00
Lokesh Vutla
5cd1f6bd7a ARM: keystone2: Allow for board specific speed definitions
Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:43 -04:00
Suman Anna
f2a8279e76 ARM: keystone2: K2G: power-off DSP during boot
The DSPs are powered on by default upon a Power ON reset, and
they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E
during the boot in u-boot. This is not functional on K2G though.
Extend the existing DSP power-off support to the only DSP present
on K2G. Do note that the PSC clock domain module id for DSP on K2G
differs from that of previous Keystone2 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:43 -04:00
Suman Anna
4ed8b2c969 ARM: keystone2: Use macro for DSP GEM power domain
Define a macro for the DSP GEM power domain id number and
use it instead of a hard-coded number in the code that
disables all the DSPs on various Keystone2 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:42 -04:00
David Lechner
2ac07f75d1 arm: Add support for LEGO MINDSTORMS EV3
This is based on the davinci da850evm. It can boot from either the
on-board 16MB flash or from a microSD card. It also reads board
information from an I2C EEPROM.

The EV3 itself initally boots from write-protected EEPROM, so no
u-boot SPL is needed.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:40 -04:00
Nishanth Menon
606e4ac35e ARM: dts: k2g: Add support for PMMC
Enable support for PMMC the TI power processor on K2G. This processor
manages all power management related activities on the SoC and and
allows the Operating Systems on compute processors such as ARM, DSP to
offload the power logic away into the power processor. U-boot just has a
load responsibility, hence the view of the hardware from a bootloader
perspective is different from the view of hardware from a Operating
System perspective. While bootloader just loads up the firmware,
Operating Systems look at the resultant system as "hardware".

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:37 -04:00
Nishanth Menon
ec00b2e3ab ARM: keystone2: psc: introduce function to hold and release module in reset.
These are useful for modules that need to be held in reset and are
enabled for data to be loaded on to them. Typically these are
microcontrollers or other processing entities in the system.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:36 -04:00
Nishanth Menon
7ca12b9700 ARM: keystone2: psc-defs: use adequate () for macros
'#define X a | b' is better defined as '#define X (a | b)' for obvious
reasons.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:36 -04:00
Nishanth Menon
82ff21bd6f ARM: keystone2: psc: redo doc in kernel-doc format
u-boot coding style guidance in
http://www.denx.de/wiki/U-Boot/CodingStyle clearly mentions that the
kernel doc style shall be followed for documentation in u-boot.

Current PSC documentation standard does not, so fix that.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:36 -04:00
Nishanth Menon
239c6953a9 ARM: keystone2: Get rid of unused clock files
With commit fe772ebd28 ("ARM: keystone2: Use common definition for
clk_get_rate"), we have centralized the clock code into a common clock
logic and the redundant files, unfortunately remained... Clean that
up.

Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:35 -04:00
Kipisz, Steven
212f96f6bd board: ti: AM57xx: Add detection logic for AM57xx-evm
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).

The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.

Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.

NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.

This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:35 -04:00
Kipisz, Steven
d88d6c8ccf ARM: OMAP4/5: Add generic board detection hook
Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override from board files that may desire to do
so.

NOTE: All TI EVMs are capable of detecting board information based on
early clocks that are configured. However, in case of additional needs
this can be achieved within the override logic from within the board
file.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:34 -04:00
Nishanth Menon
5f8bb93b23 ti: AM437x: Use generic EEPROM detection logic
Now that we have a generic TI eeprom logic which can be reused across
platforms, reuse the same.

This revision also includes fixes identified by Dave Gerlach
<d-gerlach@ti.com>

Cc: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Steven Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:34 -04:00
Nishanth Menon
770e68c0a3 ti: AM335x: Use generic EEPROM detection logic
Use the generic EEPROM detection logic instead of duplicating the AM
eeprom logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Steven Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:33 -04:00
Lokesh Vutla
0bea813d00 ARM: omap-common: Add standard access for board description EEPROM
Several TI EVMs have EEPROM that can contain board description information
such as revision, DDR definition, serial number, etc. In just about all
cases, these EEPROM are on the I2C bus and provides us the opportunity
to centralize the generic operations involved.

The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
However, DRA-7* EVMs, OMAP4SDP use a modified format.

We hence introduce logic which is generic between these platforms
without enforcing any specific format. This allows the boards to use the
relevant format for operations that they might choose.

This module will compile for all TI SoC based boards when
CONFIG_TI_I2C_BOARD_DETECT is enabled to have optimal build times for
platforms that require this support.

It is important to note that this logic is fundamental to the board
configuration process such as DDR configuration which is needed in
SPL, hence cannot be part of the standard u-boot driver model (which
is available later in the process). Hence, to aid efficiency, the
eeprom contents are copied over to SRAM scratchpad memory area at the
first invocation to retrieve data.

To prevent churn with cases such as DRA7, where eeprom format maybe
incompatible, we introduce a generic common format in eeprom which
is made available over accessor functions for usage.

Special handling for BBG1 EEPROM had to be introduced thanks to the
weird eeprom rev contents used.

The follow on patches introduce the use of this library for AM335x,
AM437x, and AM57xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:33 -04:00
Kipisz, Steven
725700dcbf ARM: OMAP4/5: Centralize gpi2c_init
Centralize gpi2c_init into omap_common from the sys_proto header so
that the information can be reused across SoCs.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:32 -04:00
Kipisz, Steven
93e6253d11 ARM: OMAP4/5: Centralize early clock initialization
Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.

By splitting up prcm_init and centralizing this clock initialization,
we setup the code for follow on patches that can do board specific
initialization such as board detection which will depend on these
basic clocks.

As part of this change, since the early clock initialization
is centralized, we no longer need to expose the console clock
initialization.

NOTE: we change the sequence slightly by initializing console clocks
timer after the io settings are complete, but this is not expected
to have any functioanlity impact since we setup the basic IO drive
strength initialization as part of do_io_settings.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:32 -04:00
Simon Glass
73223f0e1b Kconfig: Move CONFIG_FIT and related options to Kconfig
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.

Move these options to Kconfig and tidy up board configuration:

   CONFIG_FIT
   CONFIG_OF_BOARD_SETUP
   CONFIG_OF_SYSTEM_SETUP
   CONFIG_FIT_SIGNATURE
   CONFIG_FIT_BEST_MATCH
   CONFIG_FIT_VERBOSE
   CONFIG_OF_STDOUT_VIA_ALIAS
   CONFIG_RSA

Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.

Note: Masahiro's moveconfig.py script is amazing.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:07 -04:00
Peng Fan
00b1d2d317 imx: mx6: hdmi: handle overflow condition
If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-14 22:53:45 +01:00
Simon Glass
3f603cbbb8 dm: Use uclass_first_device_err() where it is useful
Use this new function in places where it simplifies the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 15:34:50 -06:00
Jacob Chen
8530783594 rockchip: video: Add LVDS support in vop driver
LVDS have a different display out mode, add code to get right flag.

The vop_ip decide display device and the remote_vop_id decide which
vop was being used. So we should use the remote_vop_id to set DCLK_VOP.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:24:10 +01:00
Jacob Chen
cfd9794115 rockchip: dts: Add LVDS support
Add these node to be used in rockchip LVDS and VOP driver.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:12:15 +01:00
Jacob Chen
35ac89dd8f rockchip: video: Add a display driver for rockchip LVDS
Some Rockchip SoCs support LVDS output. Add a display driver for this so
that these displays can be used on supported boards.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:06:33 +01:00
Simon Glass
9e971632cd freescale: Remove CONFIG_DM from header files
Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP
relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA.
Remove the hacks which enable CONFIG_DM in header files and update the
defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 14:21:27 -04:00
Tom Rini
cf77f6ffd9 Merge git://git.denx.de/u-boot-rockchip 2016-03-10 10:55:06 -05:00
Chris Zhong
b5788dc0dd rockchip: rk3288: correct sdram setting
The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
and it expects uboot to store the value using a same protocol. But now
the ddr setting value is different with DMC, so if you enable the DMC,
system would crash in kernel. Correct the sdram setting here, according
to the requirements of kernel.

[0]
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/
chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-10 08:32:01 -07:00
FUKAUMI Naoki
87cef34576 rockchip: make configure_emmc() empty for Firefly-RK3288
on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for
Firefly-RK3288. (it's fine for Rock2)

$ gcc --version
gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

$ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin u-boot-spl-dtb.img
Warning: SPL image is too large (size 0x80d0) and will not boot

to reduce size of SPL image, this patch makes configure_emmc() empty for
Firefly-RK3288 as same as Rock2.

Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
2016-03-10 08:32:01 -07:00
Lin Huang
99aaa93075 rockchip: rk3036: change ddr frequency to 400M
emac may use dpll as clock parent, and it request the clock frequency
multiples of 50, so change ddr frequency to 400M.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-10 08:32:01 -07:00
Fabio Estevam
e25a0656ba mx7: Distinguish between dual and solo versions
Read the number of cores in the fuses to distinguish between
the dual and solo versions.

Tested on a mx7d sabresd and on a mx7solo warp7.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-09 12:50:39 +01:00
Akshay Bhat
f9162b15c1 arm: imx: Add support for GE Bx50v3 boards
Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-09 12:45:42 +01:00
Matthias Schiffer
499b847521 MIPS: fix mips_cache fallback without __builtin_mips_cache
The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-03-09 11:00:40 +01:00
Tom Rini
699946ae61 sandbox: Fix building with LLVM
- The macro __BIGGEST_ALIGNMENT__ is gcc-specific.  If it is not defined
  we'll just assume 16.  This is correct for at least the common cases
  and LLVM does not provide an equivalent macro.
- When linking U-Boot we're passing -T to the linker, and while gcc will
  just pass this along with LLVM we need to be specific.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-08 15:01:46 -05:00
Alexander Graf
22d90d560a omap3: Use raw SPL by default for mmc1
Now that we fall back to the FS code path when we don't find u-boot
at the raw sector offset, there is no good reason to not default to
raw boot.

With this patch, I can successfully boot u-boot from a raw sector
offset on beagle-xm.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-08 15:01:46 -05:00
Masahiro Yamada
5d07648662 ARM: uniphier: allow debug_ll_init() to do nothing for unknown SoCs
This function should just return for unknown SoCs rather than writing
unexpected values to registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-09 01:11:15 +09:00
Masahiro Yamada
51244a6080 ARM: uniphier: fix build error when CONFIG_CMD_DDRMPHY_DUMP=y
The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit
46abfcc99e ("ARM: uniphier: rework struct uniphier_board_data").

Fixes: 46abfcc99e ("ARM: uniphier: rework struct uniphier_board_data")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-09 01:10:47 +09:00
Bhuvanchandra DV
fc9e8f2817 colibri-vf: Disable pull-up configuration in GPIO pin mux
During very early boot-ROM execution the pinmux
configuration isi in Hi-Z state. If pull-up is enabled
on GPIO pad's there will be a short period of toggle
from high to low on the IO when GPIO is set low during
boot. To avoid this glitch, disable pull-up configuration
in GPIO pinmux.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2016-03-02 14:47:16 +01:00
Paul Kocialkowski
23a004a63f sniper: Various minor cleanups, missing Kconfig configs and reorganisation
This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-29 14:49:37 -05:00
Yuichiro Goto
ba10b852fe ARM: start.S: fix typo
Fix typo in comment about position of 'A' bit in several start.S.

Signed-off-by: Yuichiro Goto <goto.yuichiro@espark.co.jp>
2016-02-29 14:49:35 -05:00
Masahiro Yamada
11d3ede42c ARM: uniphier: fix warnings reported by aarch64 compiler
The UniPhier SoC family has not supported ARMv8 yet, but these would
cause warnings if they were compiled with a 64bit compiler.  Before
adding the ARMv8 support really, fix them now.

Because UniPhier SoCs do not support Large Physical Address Extension,
casting "phys_addr_t" into "unsigned long" would carry the address
as is.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-01 00:33:29 +09:00
Masahiro Yamada
fe5ea57bdb ARM: uniphier: prepare directory structure for ARMv8 SoC support
Before adding ARMv8 support, this commit refactors the directory
structure.  Move ARMv7 specific files to arch/arm/mach-uniphier/arm32
to avoid a mess by mixture of ARMv7 and ARMv8 code.  Also move the
"select CPU_V7" to the lower-level menu because we will have to
select ARM64 instead of CPU_V7 for ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-01 00:33:24 +09:00
Masahiro Yamada
2247c332db ARM: uniphier: rename PH1-LD10/PH1-sLD11 to PH1-LD20/PH1-LD11
Due to the company's awful projecting, PH1-LD10 and PH1-sLD11 have
been renamed to PH1-LD20 and PH1-LD11, respectively.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
5fb87a1632 ARM: uniphier: rework UniPhier SoC select in Kconfig
The chains of "depends on <SoC_name>" in the current Kconfig is
clumsy.  The idea here is to allow users to choose a SoC group first
(SoC group consists of some SoCs that can coexist in one binary).
Then, allow to enable/disable each SoC support in the selected SoC
group.  This makes the Kconfig menu clearer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4e651003e5 ARM: uniphier: rename variable for DRAM controller base address
Rename the variable that contains the base address for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a191e0dee0 ARM: uniphier: deprecate umc_dram_init_{start, poll}
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
7c9cac9c22 ARM: uniphier: remove unused macros for UMC base addresses
These macros are no longer used.  These base addresses are
SoC-dependent, so they should not be placed in the header.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
fd14397e93 ARM: uniphier: rework DRAM size handling in UMC init code
Currently, DRAM size is converted twice:
  size in byte -> size in Gbit -> enum

Optimize the code by converting the "size in byte" into enum directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
9a71844a38 ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
b870848795 ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c5985b4bbb ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
71d7ef35df ARM: uniphier: refactor UMC init code for PH1-LD4
Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
380a8cafc0 ARM: uniphier: support more DRAM use cases for PH1-sLD8
Support DDR3-1600 / 512MB DDR size.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
82e5950802 ARM: uniphier: refactor UMC init code for PH1-sLD8
Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
6257a0b0e9 ARM: uniphier: refactor DDR-PHY init code
The if-else statements for the frequency-dependent register settings
seem clumsy.  Moving them to arrays would make it cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
7887670498 ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()
The DDR PHY settings no longer depend on the DRAM size.  Drop the
argument from the init function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4f19f61184 ARM: uniphier: merge DDR PHY init code for 3 SoCs
Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4021b4381d ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3.  It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).

Default DDR3 spec for each SoC:

  PH1-LD4, PH1-sLD8: DDR3+
  Others: DDR3

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
3c963d4899 ARM: uniphier: disable debug circuit clocks for PH1-Pro4
These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
00dd3f6ab0 ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings
These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
94b756f331 ARM: uniphier: refactor UMC init code for ProXstream2
Currently, a dummy value is defined for the UMC_SPCCTLA register
when the DRAM size is zero.  This seems weird because the controller
does not need setting in the first place if the size is zero.

Also, redefine enum dram_size to represent the DRAM size per 16-bit
unit.  This makes things simpler because the channel 0 and 1 are
connected with 32-bit width DRAM, while the channel 2 is connected
with 16-bit width one.

I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_*
for consistency) while I am here because SIZE_* might be easily
mixed-up with the macros in include/linux/sizes.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a54c879a42 ARM: uniphier: use pr_err() where possible
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
59fe23c2e0 ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
46abfcc99e ARM: uniphier: rework struct uniphier_board_data
This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it.  It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
8353266825 ARM: uniphier: remove unused umc_polling()
This function is unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
aa8a93480e ARM: uniphier: default to environment in eMMC
Of the several boot devices supported, it looks like the eMMC is the
most commonly used.  Enable CONFIG_ENV_IS_IN_MMC by default.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
569e4be172 ARM: uniphier: add a command to find the first MMC (non-SD) device
UniPhier SoC family supports both (e)MMC boot and SD card boot;
however, both of them are handled in the same uclass.

When booting from the eMMC, we want to know the device number
of the (e)MMC, not SD.  This command is useful to find the first
MMC (non-SD) device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a55d9feeec ARM: uniphier: add eMMC boot support
Export device nodes needed for eMMC boot (eMMC node, pinctrl, and
clock) to the SPL DTB.  CONFIG_SUPPORT_EMMC_BOOT is also necessary
to use "mmc partconf" command.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c7f94eecfd ARM: dts: uniphier: add SD/MMC host controller nodes
This host controller is available for all UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4aceb3f8d4 ARM: uniphier: enable UniPhier SD/MMC host driver
Enable the driver in all UniPhier defconfig files and add some
needed defines to the common files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
595dc1e162 ARM: dts: uniphier: add GPIO controller nodes
Make the GPIO driver really active.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
b800cbde4f ARM: uniphier: enable GPIO command and driver for UniPhier SoCs
This allows to use the "gpio" command.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
f8facbe71e gpio: do not include <asm/arch/gpio.h> for UniPhier
I implemented a GPIO driver based on Driver Model for the UniPhier
SoC family, but I could not find any good reason why such SoC
specific GPIO headers are needed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
0f5fb8ce40 ARM: dts: uniphier: rework System Bus nodes
Follow the changes of DTS in Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Tom Rini
cdb714d7c9 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2016-02-24 18:44:19 -05:00
Tom Rini
e1417c7b66 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-02-24 18:44:15 -05:00
Michal Simek
20434c8a0b microblaze: Add missing chosen node
fdtgrep requires /chosen node to be specified or at least more nodes which
stays in DTS to generate output.
Error message:
./tools/fdtgrep -b u-boot,dm-pre-reloc -RT dts/dt.dtb -n /chosen -O
dtb | ./tools/fdtgrep -r -O dtb - -o spl/u-boot-spl.dtb -P pinctrl-0 -P
pinctrl-names -P clocks -P clock-names -P interrupt-parent
Error: FDT_ERR_BADMAGIC

This patch add empty chosen node to keep fdtgrep happy and pass
compilation for in tree DTS file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-24 18:44:15 -05:00
Lubomir Rintel
757cd149b9 rpi: set board serial number in environment
Gets propagated into the device tree and then into /proc/cpuinfo where
users often expect it.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
2016-02-24 18:44:12 -05:00
Vikas Manocha
e66c49fa93 stm32: add support for stm32f7 & stm32f746 discovery board
This patch adds support for stm32f7 family & stm32f746 board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-02-24 18:43:57 -05:00
Vikas Manocha
09959ba3c5 gpio: stm32_gpio: move base addresses to the soc file
Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-02-24 18:42:50 -05:00
Vikas Manocha
14cec06113 gpio: stm32_gpio: move clock config from driver to board
This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-02-24 18:42:49 -05:00
Marek Vasut
e6e34ca3ad arm: socfpga: Fix ethernet reset handling
The following patch caused cpu_eth_init() to not be called anymore
for DM-capable boards:

commit c32a6fd07b
Date:   Sun Jan 17 14:51:56 2016 -0700
    net: Don't call board/cpu_eth_init() with driver model

This breaks ethernet on SoCFPGA, since we use that function to un-reset
the ethernet blocks. Invoke the ethernet reset function from arch_misc_init()
instead to fix the breakage.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
2016-02-24 19:13:03 +01:00
Marek Vasut
80da86642b arm: socfpga: Remove bashisms from qts filter
Weed out bashisms from the script. The echo -e does not work in dash,
which is the default /bin/sh in debian .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
2016-02-24 19:13:03 +01:00
Marek Vasut
755ff3a38d arm: socfpga: cv_socdk: Add support for QSPI boot
Add missing DT nodes to allow booting from QSPI NOR.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
2016-02-24 19:13:03 +01:00
Marek Vasut
a1d4e962ca arm: socfpga: av_socdk: Add support for QSPI boot
Add missing DT nodes to allow booting from QSPI NOR.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
2016-02-24 19:13:03 +01:00
Alison Wang
a08b1921b4 armv7: ls102xa: Move smmu and stream id initialization into the common soc code
The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:15 -08:00
Qianyu Gong
0e52b6fea1 armv8/fsl-layerscape: fdt: add fixup for Fman ucode
Add fdt fixup to insert Fman firmware into the device tree.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:14 -08:00
Qianyu Gong
075affb1ac fm: fdt: Move fman ucode fixup to driver code
Not only powerpc/mpc85xx but also Freescale Layerscape platforms will
use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device
tree. So move the function to Fman driver code.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:13 -08:00
Qianyu Gong
2459afb1a7 qe: move drivers/qe/qe.h to include/fsl_qe.h
As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:13 -08:00
Mingkai Hu
bbc8e053ba armv8/ls1043a: Implement workaround for erratum A009660
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:56 -08:00
Shengzhou Liu
3e0a0fbbac armv8/ls1043a: enable workaround for errarum A009942
DDR erratum A-009942 applies to LS1043A.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:56 -08:00
Aneesh Bansal
f698e9f39a powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.

The patch reverts commit 7cad2e38d6.

The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:55 -08:00
York Sun
2f7d70082c arm: ls1021aqds: Enable driver model lpuart serial driver
Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart
to driver model suport. Enable lpuart port driver.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
2016-02-24 08:40:15 -08:00
Tom Rini
52dd704bf8 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-02-23 15:35:47 -05:00
Jelle van der Waa
dc44fd8ae4 sunxi: H3: Add support for the host usb-phys
Add support for phy 1-3.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-02-23 20:59:10 +01:00
York Sun
d83b47b778 arm: ls1021aqds: Convert to driver model and enable serial support
Split duart configuration as device tree file. Move /chosen node
out of board commone device tree. Convert ls1021aqds nor and SD
configurations to driver model support (qspi already uses DM).
Enable ns16550 DM serial driver for nor configurations.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
2016-02-23 08:08:15 -08:00
Michal Simek
baec7df738 ARM: zynq: Add reset-gpio property for USB on Zybo
DTS syncup with Linux kernel.
Add missing reset-gpio property.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-22 16:37:50 +01:00
Nathan Rossi
cb204a69d6 ARM: zynq: Enable u-boot,dm-pre-reloc for qspi
Enable u-boot,dm-pre-reloc for qspi for zc706, zed and microzed.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-22 16:21:05 +01:00
Michal Simek
e832a142b9 ARM: zynq: Remove unused SPI base addresses
Remove unused macros. Adresses are taken from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
2016-02-22 16:20:59 +01:00
Tom Rini
595af9db24 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-02-21 07:56:16 -05:00
Peng Fan
35c4ce5e20 imx: mx7d: isolate resources to domain 0 for A7 core
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.

So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.

This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
83703a1ccf imx: mx7: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
0623d375cf imx: mx6: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
6f6058bfd8 imx: imx-common: introduce boot auxiliary core
To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".
Introduce Kconfig option IMX_BOOTAUX.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
677656bdb5 imx: mx7d: clock support for RDC
If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
af0135928e imx: mx7d: Add RDC support
Add the peripherals/masters definitions and registers base addresses
for mx7d RDC.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
d08607e1e7 imx: mx6sx Add RDC mappings of masters and peripherals
Add the definitions for the RDC mappings for i.MX6 SoloX.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
de09c43bbf imx: imx-common: introduce Resource Domain Controller support
Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:26 +01:00
Peng Fan
613e01065a imx: mx6: introduce rdc regs
Introudce rdc regs structure and rdc sema reg structure for i.MX6.
For now, to i.MX6, only i.MX6SX supports this.

Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-02-21 11:46:25 +01:00
Soeren Moch
1a43dc11a3 imx: mx6: Implement mmc_get_env_part
commit 216d286c7e [imx: mx6: implement
mmc_get_env_dev] introduced selection of the environment device according
to the boot device when booting from SD/MMC.

Extend this functionality for also selecting the device partition.

Signed-off-by: Soeren Moch <smoch@web.de>
2016-02-21 11:31:44 +01:00
Ulises Cardenas
f91e65a74e imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7
Refactored data structure for CAAM's job ring and Secure Memory
to support i.MX7.

The new memory map use macros to resolve SM's offset by version.
This will solve the versioning issue caused by the new version of
secure memory of i.MX7

Signed-off-by: Ulises Cardenas <raul.casas@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-21 11:20:54 +01:00
Bin Meng
a2e3b05e16 x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
87077e97d1 x86: ivybridge: bd82x6x: Support FSP enabled configuration
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
dc5be508b0 x86: fsp: Make sure HOB list is not overwritten by U-Boot
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
4374139627 x86: ivybridge: Add FSP support
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Stephen Warren
4fd64d02b2 x86: fix memalign() parameter order
Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)

Fixes: 45b5a37836 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-21 13:42:51 +08:00
Tom Rini
20680b560a Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-02-20 17:32:48 -05:00
Alexey Brodkin
db6ce2312d arc: cache - utilize IO coherency (AKA IOC) engine
With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.

With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-02-20 11:20:05 +03:00
Alexey Brodkin
379b3280b3 arc: cache - accommodate different L1 cache line lengths
ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.

Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.

With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-02-20 11:19:53 +03:00
Gregory CLEMENT
522e4fbb76 ARM: Add Support for the VInCo platform
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[rebase on current TOT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-19 15:12:13 +01:00
Samuel Mescoff
f7cf291aa7 ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.

Based on the commit b5ea95ef2b5b from the at91bootstrap repository.

Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:41 +01:00
Marek Vasut
c21c28b6f3 arm: at91: Add support for DENX MA5D4 SoM and EVK
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the
Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI
CAN controllers and DRAM, the baseboard contains UART connectors,
ethernet port, microSD slot, LCD header, 2x CAN connector and a
lot of expansion headers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:41 +01:00
Wenyou Yang
c43a72e88e ARM: at91: clean up the PMC_PLLICPR init code
Due to introducing the PMC_PLLICPR init function, use this
function to clean up the code.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:41 +01:00
Wenyou Yang
c0b868c087 ARM: at91: clock: add PMC_PLLICPR init function
To avoid the duplicated code, add the PMC_PLLICPR init function.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:41 +01:00
Wenyou Yang
be5e485cf9 ARM: at91: clock: add PLLB enable/disable functions
To avoid the duplicated code, add the PLLB handle functions.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
[add enable/disable functions to arm920t]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:41 +01:00
Wenyou Yang
db5c102be2 ARM: at91: armv7: clean up UTMI PLL handle code
Due to introducing the UTMI PLL enable function, use this function
to reduce the duplicated code.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:40 +01:00
Wenyou Yang
1e70b37346 ARM: at91: clock: add UTMI PLL enable/disable function
To avoid the duplicated code, add the UTMI PLL handle functions,
and add PMC_USB init function too.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:40 +01:00
Wenyou Yang
eced5a7eb4 ARM: cpu: at91: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to clean up the duplicated code.

Meanwhile, remove unneeded header file include, at91_pmc.h.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fixup for arm920t code]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:40 +01:00
Wenyou Yang
41bf25c2e1 ARM: at91: clock: add a new file to handle clock
To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM core.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:40 +01:00
Wenyou Yang
e5322df4e7 ARM: at91: asm/at91_pmc.h: fix trival register offset
Remove unnecessary #ifdef CPU_HAS_PCR.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18 21:34:40 +01:00
Stephen Warren
5589bc2770 ARM: tegra: enable USB device mode port on Dalmore
This allows U-Boot to expose UMS and DFU protocols on this port in device
mode, or to act as a USB host on the port, using an "OTG" (micro-B to
female A host) cable.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-18 10:02:19 -07:00
Simon Glass
d6ef8a6194 video: tegra: Correct a Kconfig warning with VIDCONSOLE_AS_LCD
This new feature causes a Kconfig warning on boards without a display
enabled. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-17 13:36:16 -07:00
Simon Glass
e007633b00 tegra: video: Clean up the old LCD/PWM driver code
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we
are using driver model for video.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:53 -07:00
Simon Glass
91c08afe66 tegra: video: Move LCD driver to use the DM PWM driver
Use the driver-model PWM driver in preference to the old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:53 -07:00
Simon Glass
bfda03770c tegra: video: Move LCD enums into the driver
There is no need to have these in a separate file as they are not
referenced from anywhere else.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:53 -07:00
Simon Glass
9e6866d3b6 tegra: video: Convert tegra20 LCD driver to driver model
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.

Boards which use this are fixed up, but only seaboard is tested.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:52 -07:00
Simon Glass
ce0c474a72 tegra: video: Merge the two config structures together
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:52 -07:00
Simon Glass
71cafc3fba tegra: video: Merge the display driver into one file
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.

Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:52 -07:00
Simon Glass
ee7d755a58 tegra: dts: Sync tegra20.dtsi with Linux v4.4
This file has changed quite a bit since it was set up. Sync it back with
Linux v4.4. Adjust the users slightly to cope with the changes:

- the host1x node is now called host1x@50000000
- we need a clocks node to provide the clk32k_in phandle
- active usb nodes need status = "okay"
- active i2c nodes need status = "okay"

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:51 -07:00
Simon Glass
d2f906500e tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20
This option refers only to the tegra20 video driver, so name it as such
to avoid confusion with tegra124.

Also move this option to Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:51 -07:00
Simon Glass
135a87ef43 tegra: Allow CONFIG_DM_VIDEO to be used as well as CONFIG_LCD
While we transition to using driver model for video, we need to support both
options.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:51 -07:00
Simon Glass
3f2997a40c tegra: Allow driver model to be used for the PWM
We can skip this manual init when using driver model for the PWM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:51 -07:00
Simon Glass
4dd811581a tegra: lcd: Merge tegra124-lcd.c into display.c
There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:51 -07:00
Simon Glass
7429b9623b tegra: pwm: Add a driver for the tegra PWM
This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:50 -07:00
Simon Glass
300e235378 tegra: dts: Sync up nyan-big files with Linux
Sync up these files with Linux v4.4. Some differences remain, principally
that the addresses are still 32-bit in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:50 -07:00
Simon Glass
f4abbee3ae tegra: dts: Sync up the tegra124 device tree files with Linux
Sync up these files with Linux v4.4.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16 09:17:50 -07:00
David Müller (ELSOFT AG)
26275dae82 arm: build some file(s) as ARM mode only
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15 12:04:46 -05:00
David Müller (ELSOFT AG)
02499e4edc arm: the ARM920T is THUMB capable, so select the appropriate ISA
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15 12:04:45 -05:00
David Müller (ELSOFT AG)
03a3a8aec8 arm: make sure board_init_r() is being called using the right mode (ARM / THUMB)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-15 12:04:45 -05:00
Tom Rini
823ecd72bb Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-02-14 08:39:32 -05:00
Masahiro Yamada
3f23111722 ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boards
Initial commit for PH1-Pro4 Ace and Sanji boards.

Note:
There are two variants for the Ace board in terms of the amount of
DDR memory; 1GB or 2GB.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
500aacabef ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board
This is used for on-board inter-connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
a65256d304 ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board
This board has an EEPROM connected to the I2C channel 0 of the SoC.
Its slave address is 0x54.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
f775c09d00 ARM: uniphier: adjust DDR clock delay line for ProXstream2
It turned out that DDR channel 2 was not working on ProXstream2
Vodka board.  Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
c9552895a8 ARM: uniphier: move cmd_ddrmphy.c to fix build error
If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails.

Fixes: 93d92d46cd ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
126f9bad77 ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.c
The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram
to build these commands.

Fixes: 93d92d46cd ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
2851971b8f ARM: uniphier: remove unused header mio-regs.h
This header is no longer used.

This is the last file in arch/arm/mach-uniphier/include/mach/.
At last, I've succeeded in eliminating the mach directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
8034b5171f ARM: uniphier: drop unneeded EHCI pin mux settings
These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
cd0847fe63 ARM: uniphier: switch over to generic EHCI driver
The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.

Since commit 4feefdcfe9 ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.

We no longer need to stick to the dedicated driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:51:07 +09:00
Masahiro Yamada
49dde45ba8 ARM: dts: uniphier: add clocks properties to EHCI nodes
This allows the EHCI driver to get clocks from device tree.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
aa37aba128 ARM: dts: uniphier: add device nodes for MIO control block
This block provides clock and reset control for MIO (Media I/O)
hardware blocks such as USB2.0, SD card, eMMC, etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
9fbb2f7ec6 ARM: dts: uniphier: add device nodes for Peripheral control block
This block provides clock and reset control for peripherals such as
UART, I2C, IC card, etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
233812a642 ARM: dts: uniphier: add device nodes for System Control blocks
These are mainly used for controlling clocks and resets.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
cc33609546 ARM: dts: uniphier: add reference clock nodes
Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
48264d9beb clk: uniphier: add Media I/O clock driver for UniPhier SoCs
This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
fec4816387 ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC
The USB boot code is too fat and complicated to be included in SPL
(at least for now).  So, it was implemented as a separate project
(what we call USB-loader).

The expected boot sequence is as follows:

  Boot ROM -> USB-loader -> SPL -> U-Boot proper

The USB-loader loads the SPL and U-Boot proper from a USB memory
onto the locked L2 cache.  Then, SPL needs to copy the U-Boot proper
to DRAM, so this mode looks like a NOR boot from the view of SPL.
However, we want to distinguish between (genuine) NOR boot and USB
boot in some places.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
a89be270e7 ARM: uniphier: add missing static qualifier
This function is for local use in the file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
4b50369fb5 ARM: uniphier: create early page table at run-time
UniPhier SoCs are not equipped with dedicated on-chip SRAM.  Instead,
locked outer cache is used as RAM area during the early boot stage
where DRAM is not ready yet.  This effectively means MMU must be
always enabled while we are in SPL.

Currently, the SPL image for UniPhier SoCs contains the page table
statically defined at compile time.  It has been a burden because the
16KB page table occupies a quarter memory footprint of the 64KB SPL
image.

Finally, there is no more room to implement new features in SPL.
Setting aside the NOR boot mode, this issue can be solved by creating
the page table onto RAM at run time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
755c7d9a61 ARM: uniphier: change stack pointer address for SPL
No special reason for the current stack address 0x0ff08000.
Change it to 0x00100000 to simplify the init_page_table.

There are two types of SoCs in terms of the load address of SPL.

 [1] PH1-sLD3, PH1-LD4, PH1-sLD8
   SPL is loaded at 0x00040000-0x0004ffff
 [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b
   SPL is loaded at 0x00100000-0x0010ffff

The new stack area (0x000f8000-0x00100000) should be safe for all the
cases.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
494456bc67 spl: define BOOT_DEVICE_USB
This enum is referenced from common/spl/spl.c.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
84a7562e49 ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boards
Some of PH1-Pro4 boards are equipped with larger amount of DRAM than
the reference board.  Add UMC settings to support them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Siva Durga Prasad Paladugu
78cb965af0 zynqmp: nand: Add Nand driver support for zynqmp
Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-12 17:27:28 -06:00
Tom Rini
9ef2835f26 Merge branch 'master' of git://git.denx.de/u-boot-video 2016-02-11 18:18:15 -05:00
Simon Glass
6c88b51305 video: tegra: Enable the 'lcd' env variable work-around
Enable this option on all tegra boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2016-02-11 21:39:38 +01:00
David Müller (ELSOFT AG)
928f605455 Remove unused CONFIG_MODEM_SUPPORT option and associated dead code.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-08 10:22:44 -05:00
Mugunthan V N
2c5bf6c98d ARM: dts: k2g: Add keystone net dts files
Add keystone net DT support for k2g evm.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-08 10:10:48 -05:00
Adam Ford
2cd1ff8403 OMAP3_LOGIC: Setup defconfig to enable SPL and NAND booting
The defconfig patch will enable the the SPL and NAND settings.
The update to Kconfig will allow the SPL to configured in and
built.

Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-08 10:10:39 -05:00
Vikas Manocha
dffceb4b15 serial: serial_stm32: move clock config from driver to board
This patch removes the uart clock enable from serial driver & move it in the
board code.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-08 10:10:36 -05:00
Tom Rini
57dc53a724 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2016-02-08 09:48:04 -05:00
Tom Rini
7b6dc11c1a Merge branch 'master' of git://git.denx.de/u-boot-nios 2016-02-08 09:39:54 -05:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Thomas Chou
e4f348ba6f nios2: set up the debug UART early
Set up the debug UART early if enabled, so that it is ready to use.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
2016-02-06 15:14:25 +08:00
Bin Meng
5c884420a5 x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:24 +08:00
Bin Meng
d8277a87d0 x86: Disable DM_PCI_COMPAT
Now that all x86 codes have been converted to use proper DM PCI APIs,
it's time to disable the legacy compatible layer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-05 12:47:24 +08:00
Bin Meng
5a257df702 x86: quark: Use Quark's own PCI config APIs
There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:23 +08:00
Bin Meng
3857ed015f x86: pci: Drop legacy PCI APIs
Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:23 +08:00
Bin Meng
58316f9b9f x86: pci: Use DM PCI APIs in pci_assign_irqs()
Drop legacy PCI APIs usage in pci_assign_irqs() as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
6039200c65 x86: qemu: Convert to use DM PCI API
Use pci_[read|write]_config intead of x86_pci_[read|write]_config.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
66484f0fc0 x86: tnc: Remove IGD and SDVO devices from driver model
With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.

To fix this, manually remove these two devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
2b94d9fca2 x86: tnc: Use DM PCI API in disable_igd()
Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
9e36c53dd0 x86: tnc: Change disable_igd() to have a return value
So far disable_igd() does not have any return value, but we may need
that in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
248c4faa9f x86: irq: Convert to use DM PCI API
Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
b46c2088da x86: irq: Move irq_router to a per driver priv
At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
819133d9f5 x86: irq: Get irq_router's bdf via dm_pci_get_bdf()
There is no need to parse PCH's <reg> property as we have already
a DM PCI API dm_pci_get_bdf() that can handle this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
e75711a4bf x86: minnowmax: Drop io-base property in the pch_pinctrl node
IOBASE is now obtained from PCH driver, drop this <io-base> property.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:22 +08:00
Bin Meng
2b7ff26115 x86: Drop asm/arch/gpio.h
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
3ddc1c7bd3 x86: ich6_gpio: Convert to use proper DM API
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
ec2af6f82d x86: pch: Implement get_gpio_base op
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
3e389d8ba6 dm: pch: Rename get_sbase op to get_spi_base
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
d02be99e67 dm: pch: Remove pch_get_version op
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
254e677925 x86: quark: Drop unprotect_spi_flash()
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
efd633ccdd x86: tnc: Drop unprotect_spi_flash()
Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
1f9eb59d27 spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Peng Fan
216d286c7e imx: mx6: implement mmc_get_env_dev
Implement mmc_get_env_dev, devno can be got from smbr1 of SRC.
Introduce a weak function board_mmc_get_env_dev, different
boards can implement it according to different sdhc controllers
that used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-04 10:13:49 +01:00
Peng Fan
62d8cce9f3 imx: mx7dsabresd: move mmc_get_env_devno to soc code
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-04 10:13:45 +01:00
Bhuvanchandra DV
f8aaade7f3 arm: pcm052: Add device tree file's
- Add device tree files for Phytec phyCORE-Vybrid Board.
- Enable lpuart support for Phytec phyCORE-Vybrid Board.
- Use UART1 for stdout.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02 21:36:09 +01:00
Bhuvanchandra DV
987dd5f7c2 arm: vf610-twr: Add device tree file's
- Add device tree files for NXP/Freescale VF610 Tower Board.
- Enable lpuart support on NXP/Freescale VF610 Tower Board.
- Use UART1 as stdout.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02 21:36:09 +01:00
Bhuvanchandra DV
c720ff12f8 arm: colibri-vf: Enable serial support
- Enable lpuart support on Toradex Colibri VF50/VF61
- Use UART0 for stdout.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02 21:36:09 +01:00
Bhuvanchandra DV
947fb97217 arm: vybrid: Update the license string
Since SPDX license is already there, drop the full one.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02 21:36:09 +01:00
Bhuvanchandra DV
d5e4f0abad arm: vybrid: Enable lpuart support
Add device tree node's for lpuart on Vybrid platform

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02 21:36:09 +01:00
Ye Li
23e2da27d3 imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation
The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-02 21:25:50 +01:00
Ye Li
9655ebdd50 imx: mx6sx: Fix issue in LCDIF clock enablement
Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always
enter the -EINVAL return.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-02 21:25:05 +01:00
Ye Li
cf94a3427a imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:04:21 +01:00
Ye Li
d4d1dd6749 mx6: soc: Add ENET2 mac address support
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:03:59 +01:00
Marek Vasut
d339f16911 arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-02 20:58:46 +01:00
Tom Rini
161b1fe745 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-02-02 07:24:52 -05:00
Tom Rini
008e61f512 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-02-02 06:51:05 -05:00
Wenyou Yang
37dadbca0c board: atmel: sama5d2_xplained: add SPL support
The sama5d2 Xplained SPL supports the boot medias: spi flash
and SD Card.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02 11:49:13 +01:00
Wenyou Yang
4245701ef5 arm: at91/spl: mpddrc: use IP version to check configuration
To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02 11:49:12 +01:00
Wenyou Yang
c2ad76c4bd arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.

Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02 11:49:12 +01:00
Wenyou Yang
7e8702a00f arm: at91/spl: mpddrc: add struct atmel_mpddrc_config
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02 11:49:11 +01:00
Ashish kumar
7711cc0a06 arm8: ls2080: Move the core errata defines out of board specific file
Valid for core A57

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01 13:59:55 -08:00
Tom Rini
d2427caf54 Merge branch 'master' of git://git.denx.de/u-boot-mips 2016-02-01 16:58:46 -05:00
Ashish kumar
2ea3a448cc armv8: ls2080a: Implement workaround for core errata 829520, 833471
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.

833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01 13:58:22 -08:00
Purna Chandra Mandal
7d514a7407 board: Enable ethernet, tftpboot support to pic32mzdask board.
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
c76eb72c43 board: add SDHCI support for PIC32MZDASK board.
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
44da3a176c board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
be961fa15b MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
9ffa7a35ef drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
32c1a6eef8 MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-01 22:14:00 +01:00
Paul Burton
05e342554e MIPS: Support dynamic I/O port base address
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Paul Burton
8ac493cd65 MIPS: Remove SLOW_DOWN_IO
CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Marek Vasut
fbb0de088b mips: cache: Bulletproof the code against cornercases
This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will do no operation, since the size is zero.

The current implementation though has a problem where such invocation will
result in a hard CPU hang. This is because under such conditions, where the
start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
will then try to iterate over the entire address space, which in itself is
wrong. But iterating over the entire address space might also hit some odd
address which will cause bus hang. The later happens on the Atheros MIPS.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
2016-02-01 22:13:24 +01:00
Daniel Schwierzeck
e26e8dc8f4 MIPS: start.S: fix and optimize instructions
Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:13:24 +01:00
Purna Chandra Mandal
a62790997f MIPS: initialize board_init_f() argument to zero.
Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:13:24 +01:00
Qianyu Gong
73a5de4c6e armv8/ls1043aqds: fix DSPI/QSPI node in dts file
Fix the lost dts info when merging patches.

Fix DSPI node for 'commit e0579a5852 ("armv8/ls1043aqds: add DSPI
support")' and QSPI node for 'commit 166ef1e90c ("armv8/ls1043aqds:
add QSPI support in SD boot")'.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01 09:11:11 -08:00
Peng Fan
397d7d5a1b arm: config: enforce -fno-pic for gcc
Android's tool chain enable the -mandroid at default.
This option will enable the -fpic, which cause uboot compilation
failure:
"
 LD      u-boot
 u-boot contains unexpected relocations: R_ARM_ABS32
 R_ARM_RELATIVE
"

In my testcase, arm-linux-androideabi-gcc-4.9 internally
enables '-fpic', so when compiling code, there will be
relocation entries using type R_ARM_GOT_BREL and .got
section. When linking all the built-in.o using ld, there
will be R_ARM_ABS32 relocation entry and .got section
in the final u-boot elf image. This can not be handled
by u-boot, since u-boot only expects R_ARM_RELATIVE
relocation entry.
arm-poky-linux-gnueabi-gcc-4.9 default does not enable '-fpic',
so there is not .got section and R_ARM_GOT_BREL in built-in.o.
And in the final u-boot elf image, all relocation entries are
R_ARM_RELATIVE.

we can pass '-fno-pic' to xxx-gcc to disable pic. whether
the toolchain internally enables or disables pic, '-fno-pic'
can work well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-31 16:32:56 +01:00
Wang Dongsheng
c5e954eccd ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.

Use readelf -t -r u-boot show us:
.__secure_start		addr: 601408e4
.__secure_end		addr: 60141460

60141140  00000017 R_ARM_RELATIVE
46	_secure_monitor:
47	#ifdef CONFIG_ARMV7_PSCI
48      ldr     r5, =_psci_vectors

60141194  00000017 R_ARM_RELATIVE
6014119c  00000017 R_ARM_RELATIVE
601411a4  00000017 R_ARM_RELATIVE
601411ac  00000017 R_ARM_RELATIVE
64	_psci_table:
66	.word	psci_cpu_suspend
...
72	.word	psci_migrate

60141344  00000017 R_ARM_RELATIVE
6014145c  00000017 R_ARM_RELATIVE
202	ldr     r5, =psci_text_end

Solutions:
1. Change absolute address to RelAdr.
   Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.

2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
   If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-31 16:32:56 +01:00
Marek Vasut
11aa6a32eb arm: cache: Implement cache range check for v7
Add code to aid tracking down cache alignment issues.
In case DEBUG is defined in the cache.c, this code will
check alignment of each attempt to flush/invalidate data
cache and print a warning if the alignment is incorrect.
If DEBUG is not defined, this code is optimized out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
2016-01-31 16:32:56 +01:00
Marek Vasut
8890c2fbe6 arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration,
which is without the S-bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
2016-01-31 16:32:56 +01:00
Marek Vasut
a592e6fb7f arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7
The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is
set, it configures TTBR0 register. This register must be configured for the
cache on ARMv7 to operate correctly.

The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the
TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor
issues which are hard to replicate, for example certain USB sticks are not
detected or QSPI NOR sometimes fails to write pages completely.

The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is
correct because the code which added the test(s) for CONFIG_ARMV7 was added
shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was
not adjusted correctly to reflect that change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
2016-01-31 16:32:56 +01:00
Tom Rini
8a36287a01 Merge git://git.denx.de/u-boot-dm 2016-01-29 13:47:38 -05:00
Stephen Warren
dd8204de15 ARM: tegra: shut down USB device controller at boot
When loading U-Boot into RAM over USB protocols using tools such as
tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
mode controller is initialized and enumerated by the host PC running
the tool. Unfortunately, these tools do not shut down the USB
controller before executing the downloaded code, and so the host PC
does not "de-enumerate" the USB device. This patch implements optional
code to shut down the USB controller when U-Boot boots to avoid leaving
a stale USB device present.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 21:01:23 -07:00
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Bin Meng
afe6462da9 arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()
eth_get_dev_by_index() is an API which is not available in driver
model. Use eth_get_dev_by_name() instead, which can also simplifly
the code logic a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:23:22 -06:00
Tom Rini
4b5a4a0535 Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-01-28 10:07:22 -05:00
Bin Meng
81aaa3d9fc x86: Correct spi node alias
With recent changes spi node was moved to a place as a subnode under
pch, so update the alias to refer to its correct place as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 13:53:30 +08:00
Miao Yan
a5dd1e6726 x86: config option for loading ACPI table from QEMU
This patch adds a config option for loading ACPI table from QEMU. When enabled,
U-Boot won't generate ACPI tables, but use those provided by QEMU.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Miao Yan
fa287b1580 x86: qemu: add the ability to load and link ACPI tables from QEMU
This patch adds the ability to load and link ACPI tables provided by QEMU.
QEMU tells guests how to load and patch ACPI tables through its fw_cfg
interface, by adding a firmware file 'etc/table-loader'. Guests are
supposed to parse this file and execute corresponding QEMU commands.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Miao Yan
a3b15a0556 x86: qemu: setup PM IO base for ACPI in southbridge
Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Miao Yan
25757220d6 x86: qemu: re-structure qemu_fwcfg_list_firmware()
Re-write the logic in qemu_fwcfg_list_firmware(), add a function
qemu_fwcfg_read_firmware_list() to handle reading firmware list.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:30 +08:00
Stefan Roese
d521197d69 x86: baytrail: Add option to disable the internal UART to setup_early_uart()
This patch adds a parameter to the function setup_early_uart() to either
enable or disable the internal BayTrail legacy UART. Since the name
setup_early_uart() does not match its functionality any more, lets
rename it to setup_internal_uart() as well in this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 13:53:30 +08:00
Tom Rini
cd85bec36d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-01-27 15:05:36 -05:00
Tom Rini
19bde0316f Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-01-27 15:05:12 -05:00
Qianyu Gong
b0f20caf65 armv8/ls1043aqds: add QSPI boot support
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:29:09 -08:00
Gong Qianyu
166ef1e90c armv8/ls1043aqds: add QSPI support in SD boot
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:28:55 -08:00
Wenbin Song
2970e14f65 armv8/ls1043aqds: Add lpuart support
Add lpuart support using the driver model.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:13:12 -08:00
Wenbin Song
8e728aa915 armv8/ls1043aqds: Spilt off board device tree
Move new /chosen node out of the board device tree.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:13:12 -08:00
Aneesh Bansal
d0a6d7ce55 secure_boot: enable chain of trust for PowerPC platforms
Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:56 -08:00
Aneesh Bansal
d041288586 secure_boot: enable chain of trust for ARM platforms
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:49 -08:00
Aneesh Bansal
0a6b2714ad secure_boot: create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:42 -08:00
Aneesh Bansal
bdc22074c5 secure_boot: split the secure boot functionality in two parts
There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
         validating and booting LINUX.

For ESBC phase, there is no difference in SoC's based on ARM or
PowerPC cores.

But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:

If Secure Boot is executed, a separate U-Boot target is required
which must be compiled with a diffrent Text Base as compared to
Non-Secure Boot. There are some LAW and TLB settings which are
required specifically for Secure Boot scenario.

ARM:
ARM based SoC's have a fixed memory map and exit conditions from
BootROM are same irrespective of boot mode (Secure or Non-Secure).

Thus the current Secure Boot functionlity has been split into
two parts:
CONFIG_CHAIN_OF_TRUST
This will have the following functionality as part of U-Boot:
1. Enable commands like esbc_validate, esbc_halt
2. Change the environment settings based on bootmode, determined
   at run time:
     - If bootmode is non-secure, no change
     - If bootmode is secure, set the following:
         - bootdelay = 0 (Don't give boot prompt)
         - bootcmd = Validate and execute the bootscript.

CONFIG_SECURE_BOOT
This is defined only for creating a different compile time target
for secure boot.

Traditionally, both these functionalities were defined under
CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement
for a separate Secure Boot target for ARM based SoC's.
CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.

Another Security Requirement for running CHAIN_OF_TRUST is that
U-Boot environemnt must not be picked from flash/external memory.
This cannot be done based on bootmode at run time in current U-Boot
architecture. Once this dependency is resolved, no separate
SECURE_BOOT target will be required for ARM based SoC's.

Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is
defining CONFIG_ENV_IS_NOWHERE

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:32 -08:00
Aneesh Bansal
74eecd820f secure_boot: include/configs: move definition of CONFIG_CMD_BLOB
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was
earlier defined in all config files. The definition has been
moved to a common file which is included by all configs.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:26 -08:00
Aneesh Bansal
ef6c55a240 secure_boot: include/configs: make secure boot header file uniform
The file fsl_secure_boot.h must be included in config file for
Secure Boot. This is not required to be protected by any macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.

The above was missing in some config files and all files have been
made uniform in this respect.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:08 -08:00
Ricardo Ribalda Delgado
80cce2629b ppc: xilinx-ppc4xx: Port to DM serial
xilinx_uartlite has been ported to DM, this patch makes the
xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new
DM driver.

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:57:11 +01:00
Michal Simek
af813acd48 ARM64: zynqmp: Add support for SD1 boot mode
SD1 boot mode is using different bootmode values.
Add support for this mode used on DC1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Siva Durga Prasad Paladugu
0a5bcc8c0d ARM64: zynqmp: Modify the SD and QSPI bootmode values
Modify the SD bootmode value to 0x3 as per latest
spec. Also add new boot mode QSPI 32 bit boot mode

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Soren Brinkmann
0d90e9d851 ARM64: zynqmp: DT: Fix UART compatible string
ZynqMP has r1p12 not r1p8. r1p12 contains break detection support.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Punnaiah Choudary Kalluri
d3fd433f07 ARM64: zynqmp: Correct the watchdog timer interrupt number
Corrected the watchdog timer interrupt number.
Origin value was for CSUPMU watchdog.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
cb9dcc6eaa ARM64: zynqmp: Fix coding style in phy node
Trivial fix.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
be6f6af1d6 ARM64: zynqmp: Add initial support for the first silicon
Add basic configuration for the first silicon.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
0785dfd8a7 ARM64: zynqmp: Use the same U-Boot version with/without ATF
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
7ebf67a34c ARM: zynq: Move spi node to aligned location
Keep nodes aligned.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Michal Simek
4691941b45 ARM: zynq: Fix all remaining zynq platform to use stdout-path
Fix console setup for all remaining zynq boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Michal Simek
e5c343dddc ARM: zynq: Clean DTSI coding style
Fix minor indentation problems.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Michal Simek
eb04ab3492 ARM: zynq: Do not select options if SPL is not enabled
Zynq setups some default options for SPL but not all targets are
enabling SPL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Michal Simek
67b2904819 ARM: zynq: Remove memory division by 2 for ECC case
For ECC case u-boot divided memory by 2 because one u-boot could be used
for both cases when ECC is off or on.
Remove this division and make sure that dts file contain the correct
memory size when ECC is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Michal Simek
85916e29df microblaze: Remove empty file - cpu.c
No need to have empty unused file in architecture code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:53 +01:00
Michal Simek
48470b7a20 microblaze: Wire-up debug_uart in asm
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:50 +01:00
Michal Simek
93768393d7 serial: uartlite: Move driver to DM
Enable SPL DM too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
2016-01-27 15:55:49 +01:00
Ricardo Ribalda Delgado
5e68f17e24 ppc: dts: Add device tree for xilix-ppc4xx-generic
Add device tree example file for xilinx-ppc440-generic and
xilinx-ppc405-generic

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:43:01 +01:00
Ricardo Ribalda Delgado
5b218ae106 mailaddr: Update mail address
The old mail address will stop working soon.
Update it all the files

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:32:05 +01:00
Ricardo Ribalda Delgado
583aefb89c xilinx-ppc440: Remove support for v5fx30teval
It is just a specialized version of xilinx-ppc440

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:32:04 +01:00
Ricardo Ribalda Delgado
70c29dcdbc ppc: xilinx-ppc405: Remove support for fx12mm
It is just a specialized version of the xilinx-ppc405

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:32:04 +01:00
Ricardo Ribalda Delgado
9ac0efd292 ppc: xilinx-ppc440: Remove support for ml507
ml507 is just a specialized version of the xilinx-ppc440-generic

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:32:04 +01:00
Stefan Roese
b20c38a973 arm: mvebu: Add support for the Armada XP theadorable board
This patch adds support for the Armada XP (MV78260) based theadorable
board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
LCD and SATA (SSD) interfaces / devices.

Two defconfigs are added:

theadorable_defconfig:
The production U-Boot version with a stripped down drivers and feature
list. This removes networking, USB and PCI support.

theadorable_debug_defconfig:
The debugging / testing U-Boot version with full support for all drivers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-01-27 07:45:43 +01:00
Tom Rini
9e4de7fd4a Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-01-26 17:45:37 -05:00
Vishnu Patekar
cd7aa27bec sunxi: Add suport for A83T based Banana-pi M3 Board
Add dts and defconfig for Banana-pi M3 board.

It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com: rename to Sinovoip_BPI_M3_defconfig/sun8i-a83t-sinovoip-bpi-m3.dts]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Vishnu Patekar
f3ad64c88c sunxi: Add support for LPDDR3 for A83T
Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T.
Mostly the timing parameters are different from DDR3.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Vishnu Patekar
f5fd8caf7f sunxi: Groundwork to support new dram type for A83T
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.

This adds groundwork to support for new DRAM type for A83T.

Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Vishnu Patekar
627b380f62 sunxi: Redundant code cleanup from a83t dram init
This removes the redundant lines of code from mctl_sys_init.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
9683945179 sunxi: Support PSCI ops on Allwinner H3
H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
ed80584f30 sunxi: Support H3 CCU security switches
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.

Configure them to enable non-secure access.

For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:05 +01:00
Chen-Yu Tsai
5823664fb8 sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3
Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.

Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.

This patch supports the new settings, and sets them to allow non-secure
access.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-01-26 16:20:04 +01:00
Tom Rini
b72ae192e3 Merge branch 'master' of git://git.denx.de/u-boot-video 2016-01-26 09:48:07 -05:00
Tom Rini
d6ea6d8876 mips: asm/io.h: Add in <linux/bug.h>
As part of the bug.h / BUILD_BUG_* clean up, this file was missed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-25 18:52:23 -05:00
Tom Rini
d82477748d Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-01-25 16:45:00 -05:00
Ashish kumar
43381474ff arch/powperpc: Fix start_align due to use of __ffs64() instead ffs64()
Incorrect DDR law was created in case of B4860qds after commit
2d2f490d. Return value of ffs64() differs from __ffs64(), eg.
    ffs64(0x80000000) = 0x20
    __ffs64(0x80000000) = 0x1f
As a result of this change, callers need to adjust the expected
return value by removing -1.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 12:30:31 -08:00
Prabhakar Kushwaha
2c0d69713c powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seq
Users migrating Freescale's PowerPC SoC U-Boot code to their custom
board, often overlook the need to execute set_liodns() and
setup_portals() being called by platform files.

So Move set_liodns() and setup_portals() to common u-boot boot
sequence

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 12:13:31 -08:00
Pratiyush Mohan Srivastava
aa4ba7f7a2 armv8: ls2040a: Add support of LS2040A SoC
Freescale's LS2040A is a another personality of LS2080A SoC
without AIOP support consisting of 4 armv8 cores.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:17 -08:00
Pratiyush Mohan Srivastava
191e3c0527 armv8: Enable all 8 DPMAC ports in LS2080A Personality
LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:17 -08:00
Shaohui Xie
c238ad0a33 armv8: fsl-layerscape: fixes lsch2 serdes registers define
Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Tang Yuantian
1ef7ac70e2 arm: ls1021a: Adjust sata register default values
Updated the default sata register values to enhance the
performance and stability.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Shengzhou Liu
a994b3deb0 driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Prabhakar Kushwaha
6f14e257c4 armv8: fsl-lsch3: fixup SYSCLK frequency in device tree
SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.

So Fixup Linux device tree from boot-loader.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Shengzhou Liu
0d3972cfcd fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:14 -08:00
Tom Rini
2218c54bc1 Merge branch 'master' of git://git.denx.de/u-boot-imx 2016-01-25 10:40:38 -05:00
Bin Meng
81b0b0d93b openrisc: Fix build errors
With kernel.org toolchain, it reports:

  CC      arch/openrisc/lib/board.o
  arch/openrisc/lib/board.c:56:2: error: 'console_init_f' undeclared here (not in a function)
  arch/openrisc/lib/board.c: In function 'board_init':
  arch/openrisc/lib/board.c:120:2: warning: implicit declaration of function 'console_init_r'
  make[1]: *** [arch/openrisc/lib/board.o] Error 1
  make: *** [arch/openrisc/lib] Error 2

Include console.h will fix this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-25 10:40:01 -05:00
Masahiro Yamada
84b8bf6d5d bug.h: move BUILD_BUG_* defines to include/linux/bug.h
BUILD_BUG_* macros have been defined in several headers.  It would
be nice to collect them in include/linux/bug.h like Linux.

This commit is cherry-picking useful macros from include/linux/bug.h
of Linux 4.4.

I did not import BUILD_BUG_ON_MSG() because it would not work if it
is used with include/common.h in U-Boot.  I'd like to postpone it
until the root cause (the "error()" macro in include/common.h causes
the name conflict with "__attribute__((error()))") is fixed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-25 10:39:59 -05:00
Tom Rini
0080931abf serial: Remove serial_putc_raw_dev
clang-3.8 reports that serial_putc_raw_dev in serial_ns16550.c is
unused.  Further investigation shows that we have 3 places that
implement this function and no callers, remove.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-25 10:39:45 -05:00
Tom Rini
6e2f153895 arm, powerpc: Update cc-version tests to check for cc-name as well
For compatibility clang will report some gcc version.  However since we
are checking gcc versions in order to then fail to build, we should
limit these tests only to when we are using gcc and not clang.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-25 10:39:44 -05:00
Peng Fan
d9699de85c imx: mx7: default enable MDIO open drain
The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:15:14 +01:00
Peng Fan
9ba18ff8ef imx: mx6ul/sx: fix mmdc_ch0 clk calculation
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.

Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:13:21 +01:00
Peng Fan
234dc63301 imx: mx6: add more entry for mxc_ccm_reg
Add more entries for structure mxc_ccm_reg.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:12:27 +01:00
Peng Fan
bedaa842ae imx: nand: update GPMI NAND driver to support MX7
Update GPMI NAND driver and BCH head file to support i.MX7

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:09:32 +01:00
Peng Fan
1fc4f80495 imx: apbh_dma: Update APBH-DMA for MX7D
Update APBH-DMA driver and head files to support i.MX7D

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:09:16 +01:00
Simon Glass
25d5352c71 x86: ivybridge: Use syscon for the GMA device
Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to work this way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
98655f3a8d x86: Set up a shared syscon numbering schema
Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
67292e4c27 x86: ivybridge: Drop the SMM-locking code
U-Boot does not support SMM yet, so we can drop this code. It is easy to
bring back when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
b2a6235920 x86: ivybridge: Drop XHCI support
This is not used on link which is the only ivybridge board. Drop this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
278d3a4444 x86: ivybridge: Drop special EHCI init
This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
1605b10032 x86: ivybridge: Sort out the calls to bridge_silicon_revision()
This function is called all over the place. Convert it use the driver model
PCI API, and rationalise the calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
a5ea3a7d4a x86: ivybridge: Move code from pch.c to bd82x6x.c
This code relates to the PCH, so we should move it into the same file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
9434c7a35d x86: ivybridge: Convert pch.c to use DM PCI API
Convert this file to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
fad12961b0 x86: ivybridge: Convert report_platform to DM PCI API
Convert these functions to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
c02a4242c8 x86: ivybridge: Convert SDRAM init to use driver model
SDRAM init needs access to the Northbridge controller and the Intel
Management Engine device. Add the latter to the device tree and convert all
of this code to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
1641bb8cc7 x86: ivybridge: Convert sdram_initialise() to use DM PCI API
Convert this function to use the the driver model PCI API. We just need
to pass in the northbridge device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
2588e71132 x86: ivybridge: Convert dram_init() to use DM PCI API
Convert the top part of the DRAM init to use the driver model PCI API.
Further work will complete the transformation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
5213f280fc x86: ivybridge: Convert enable_usb_bar() to use DM PCI API
Convert this function over to use the driver model PCI API. In this case
we want to avoid using the real PCI devices since they have not yet been
probed. Instead, write directly to their PCI configuration address.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
0c7645bde0 x86: ivybridge: Use the I2C driver to perform SMbus init
Move the init code into the I2C driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
4265abd413 x86: ivybridge: Convert lpc init code to DM PCI API
Adjust this code to use the driver model PCI API. This is all called through
lpc_init_extra().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
cdc337ed8f x86: ivybridge: Drop the special PCI driver
There is nothing special about the ivybridge pci driver now, so just use
the generic one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
4e19072907 x86: ivybridge: Move LPC init into the LPC probe() method
Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
865c24eea1 x86: ivybridge: Move lpc_enable() into gma.c
This graphics init code is best placed in the gma init code. Move the code
and drop the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
ddf10c20d2 x86: ivybridge: Use driver model PCI API in sata.c
Adjust the functions in this file to use the driver model PCI API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
01a679084b x86: ivybridge: Use the SATA driver to do the init
Instead of manually initing the device, probe the SATA device and move the
init there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
82935b751b x86: ivybridge: Drop the unused bd82x6x_init_extra()
This function does nothing now so can be dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
d46f2a68e6 x86: ivybridge: Do the SATA init before relocation
The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:39 +08:00
Simon Glass
887cba8f38 x86: ivybridge: Drop unnecessary northbridge setup
This is done by default with PCI auto-config. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:18 +08:00
Simon Glass
1a9dd221c6 x86: ivybridge: Use driver model PCI API in bd82x6x.c
Adjust most of the remaining functions in this file to use the driver model
PCI API. The one remaining function is bridge_silicon_revision() which will
need a little more work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9ed781a6ff x86: ivybridge: Move northbridge and PCH init into drivers
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
ac643e0363 x86: Bring up northbridge, pch and lpc after the CPUs
These devices currently need to be inited early in boot. Once we have the
init in the right places (with each device doing its own init and no
problems with ordering) we should be able to remove this. For now it is
needed to keep things working.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
8b674418e0 x86: Don't show an error when the MRC cache is up to date
When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.

Avoiding printing an error when this happens.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
afd5d50c12 x86: Make x86_init_cpus() static
There are no other implementations of this function, and boards that need it
can implement a CPU driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
279006db4f x86: ivybridge: Move early init code into northbridge.c
This code is now part of the northbridge driver, so move it into the same
place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
d173185d73 x86: ivybridge: Drop the dead MTRR code
This is not used and MTRRs are set up elsewhere now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
709b1902d2 x86: ivybridge: Set up the thermal target correctly
This uses a non-existent node at present. It should use the first CPU node.
The referenced property does not exist (the correct value is the default of
0), but this allows the follow-on init to complete.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9d156b5725 x86: ivybridge: Move CPU init code into the driver
Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
bba22a97a7 x86: ivybridge: Use common CPU init code
The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9fd11c7a8c x86: ivybridge: Move GPIO init to the LPC init() method
This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
fcd30cdfa8 x86: ivybridge: Move sandybridge init to the lpc probe() method
The watchdog can be reset later when probing the LPC after relocation.
Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
17e0a9ab08 x86: ivybridge: Move graphics init much later
We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
f633efa30f x86: ivybridge: Probe the LPC in CPU init
We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
2b27d20529 x86: ivybridge: Rename lpc_init() to lpc_init_extra()
In preparation for adding an init() method to the LPC uclass, rename this
existing function so that it will not conflict.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
977a591893 x86: ivybridge: Move LPC and PCH init into northbridge probe()
Move more code into the northbridge probe() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
655925a9c5 x86: ivybridge: Move northbridge init into the probe() method
Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
e40a6e3f10 x86: ivybridge: Add a driver for the bd82x6x northbridge
Add a driver with an empty probe function where we can move init code in
follow-on patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
5544757ce9 dm: x86: Add a northbridge uclass
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
858361b174 x86: ivybridge: Rename bd82x6x_init()
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
fe40bd4d8f x86: ivybridge: Move more init to the probe() function
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
788cd90864 x86: ivybridge: Move lpc_early_init() to probe()
Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00