Commit graph

6 commits

Author SHA1 Message Date
Patrick Delaunay
e70f70aa65 ram: stm32mp1: add driver
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-19 16:14:21 -04:00
Philipp Tomsich
403e9cbcd5 rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:33 +02:00
Álvaro Fernández Rojas
193030e591 ram: add RAM driver for Broadcom MIPS SoCs
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Vikas Manocha
bf1ae4426b stm32f7: sdram: move sdram driver code to ram drivers area
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:02 -04:00
Simon Glass
64ce0cad9e dm: test: Add a test for the ram uclass
Add a test to confirm that we can probe this device and get information on
the available RAM.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:32 -06:00
Simon Glass
6c51df6859 dm: Add support for RAM drivers
Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:27 -06:00