Commit graph

39828 commits

Author SHA1 Message Date
MengDongyang
fa5e2d1689 dts: rk3399: add dwc3_typec node for rk3399
rk3399 has two dwc3 controller for type-C port, add the dts node
and enable them.

Signed-off-by: MengDongyang <daniel.meng@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:41:49 -06:00
MengDongyang
923e7b44ad config: rk3399: add usb related configs
This patch to enable configs for usb module
- xhci
- ehci
- usb storage
- usb net

Signed-off-by: MengDongyang <daniel.meng@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Squashed in patch to move to Kconfig:
  https://patchwork.ozlabs.org/patch/672543/
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:40:56 -06:00
Kever Yang
f7bb27a577 usb: host: add Kconfig for USB_XHCI_ROCKCHIP
Add a Kconfig for Rockchip xhci controller.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-09-22 07:36:58 -06:00
MengDongyang
892742df1f rockchip: select DM_USB for rockchip SoC
Select DM_USB to compatible with USB DM driver model.

Signed-off-by: MengDongyang <daniel.meng@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
MengDongyang
b44566c4ce usb: xhci-rockchip: add rockchip dwc3 controller driver
This patch add support for rockchip dwc3 controller, which corresponding
to the two type-C port on rk3399 evb.
Only support usb2.0 currently for we have not enable the usb3.0 phy
driver and PD(fusb302) driver.

Signed-off-by: MengDongyang <daniel.meng@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
aa89b554b7 rk3288: add arch_cpu_init for rk3288
We do some SoC level one time setting initialization in
arch_cpu_init.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
e2e4e14536 rk_pwm: remove grf setting code from driver
We consider the grf setting for pwm controller select as the system
operation instead of driver operation, move it to soc init, let's
remove it from pwm driver first.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
12406ae247 rk_pwm: use clock framework API to get module clock
This patch use clock API instead of hardcode for get pwm clock.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix printf() to debug() nit:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Xu Ziyuan
ce26e8a1dd rockchip: use dummy byte only enable OF_PLATDATA
Add a condition to determine the rk3288_sdram_channel size.

This patch fixes read sdram_channel property failed from DT on rk3288
boards, which not enable OF_PLATDATA.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2016-09-22 07:32:22 -06:00
Kever Yang
bd218ab8e4 dts: rk3399: add pinctrl for sdmmc
This patch add pinctrl for sdcard which may not be initialized before
uboot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
ad0513828e rk3399: enable the pwm2/3 pinctrl in board init
There is no interrupt line for each PWM which used by pinctrl to get the
periph_id, so it's not able to enable the default pinctrl setting by pinctrl
framework, let's enable it at board_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
824c03332a config: evb-rk3399: enable pinctrl driver
This patch enable rk3399 pinctrl driver and gpio driver which is sub-node
of pinctrl.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
a2c08df381 pinctrl: add driver for rk3399
This patch add pinctrl driver for rk3399.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Kever Yang
c55e30eb83 rk3399: syscon: add support for pmugrf
pmugrf is a module like grf which contain some of the iomux registers
and other registers.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-09-22 07:32:22 -06:00
Jagan Teki
fe4753cbc6 configs: fsl: Move SPI/SPI-FLASH configs to defconfig
Moved FSL_QSPI/SPI/SPI-FLASH configs from include/configs
into respective used defconfigs.
- CONFIG_FSL_QSPI
- CONFIG_SPI_FLASH
- CONFIG_SPI_FLASH_BAR
- CONFIG_SPI_FLASH_STMICRO

Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 14:17:02 +05:30
Jagan Teki
21b1dd18f1 spi: Kconfig: Move FSL_QSPI entry to non-dm place
Since FSL_QSPI driver still supporting non-dm code
better to move the Kconfig from DM undefined place.

Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 14:16:28 +05:30
Siva Durga Prasad Paladugu
e0027f089b zynqmp: Remove unnnecessary board config file for dc4
Remove unnecessary board specific config file for DC4
board.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
1309f67165 ARM64: zynqmp: Use the same name for atf image everywhere
Use atf-uboot.ub image instead of atf.ub.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
0e82602375 ARM64: zynqmp: Enable CONFIG_AHCI via Kconfig
Move CONFIG_AHCI to defconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
47e60cbdf8 ARM64: zynqmp: Add support for chip ID detection
Chip ID needs to be known for loading bitstream because
U-Boot checks ID from bitstream header in BIT format.
BIN format is completely unchecked.

The chipid is get from ATF via SMC.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Siva Durga Prasad Paladugu
6b24501438 fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP
Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to ATF which route this request to
PMU FW which will take care of loading it to PL

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
5242772c51 ARM64: zynqmp: Fix USB ulpi phy sequence
It should be enough to call low(5us)->high pulse for all cases
to provide proper reset. There is no need to call high->low->high.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
48255f5276 ARM64: zynqmp: Add support for USB ulpi phy reset via mode pins
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
d58fc12eb7 ARM64: zynqmp: Add support for DFU from SPL
SPL needs to have bigger stack size because of USB.
Simple malloc needs to be disabled because dfu code requires different
allocation functions. There is no space in OCM that's why random place
in DDR is used.

BOOTD must be disabled because it is causing compilation error.

All variables are disabled and used only variables valid for DFU because
they are simple huge. Including automatic variables added by
CONFIG_ENV_VARS_UBOOT_CONFIG.
Hardcode addresses for u-boot, atf, kernel and dtb
just for SPL DFU code.

Enable SPL DFU for zcu100.
Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:21 +02:00
Michal Simek
e1024c9808 ARM: Add new BOOT_DEVICE_DFU boot mode
This enum is needed when SPL_DFU is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
3373a52283 ARM64: zynqmp: Add USB boot mode
Add USB boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
8ed31f369a ARM64: zynqmp: Move BSS location to the beginning of ram
With SPL_DFU support memory layout needs to be cleanup
that's why move bss to the start of memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
5f647c2284 spi: zynq: Use variable to remove u32 to u64 conversions
Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
This patch is using one variable to do conversion via u32 variable.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22 07:33:20 +02:00
Michal Simek
9feff385f8 ARM64: zynqmp: Fix usb_gadget_handle_interrupt routine
Function is defined in g_dnl.h and have different parameter
then it is used. This patch fixes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
7f491d7b30 ARM64: zynqmp: Force certain bootmode for SPL
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
275bd6d11f ARM64: zynqmp: Wire up both USBs available on ZynqMP
The second USB wasn't enabled. This patch fixes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:20 +02:00
Michal Simek
6ded73aa97 fpga: Add Kconfig to fpga subsystem
Add missing Kconfig to fpga subsystem to be able
to add new options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-09-22 07:33:14 +02:00
Tom Rini
bbdae1651e omap4_panda: Disable ext2/3/4 support in SPL
Pandaboard is growing again, disable EXT2/3/4 support in SPL save more
space.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-21 21:06:55 -04:00
Tom Rini
3ce750ede1 clk.h: Add <asm/errno.h>
Since we return -ENOSYS in some cases we must have <asm/errno.>
available.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-21 17:56:01 -04:00
Jagan Teki
3632c8e5ce sf: Move flags macro's to spi_flash_params{} members
This patch moves flags macro's to respective member position on
spi_flash_params{}, for better readabilty and finding the
respective member macro's easily.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Jagan Teki
de0599284f sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash
Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash code from header file.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Jagan Teki
ddc2dfbb65 sf: Remove SECT_32K
SECT_32K never used anywhere in the code.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Jagan Teki
3ac48d0e88 spi: Remove SPI_RX_FAST
Removed SPI_RX_FAST since default read for spi slaves
are always 1-wire fast read.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Jagan Teki
08fe9c294f spi: Use mode for rx mode flags
Make rx mode flags as generic to spi, earlier mode_rx is
maintained separately because of some flash specific code.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Jagan Teki
b3afb232f7 sf: Remove e_rd_cmd from param table
e_rd_cmd is maintained separately for fastest read command code,
since the read commands are computed normally this e_rd_cmd
is not required in spi_flash_params table.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Jagan Teki
edd35f712e sf: Simplify fastest read cmd code
Fastest read command code look for fastest read command
taking inputs from spi->mode_rx and flags from param table
and controller mode_rx is always been a priority.

Since mode_rx is always set from controller side this optimized
code doesn't require much and this code required exctra overhead like
1) Maintain e_rx_cmd in param table
2) Maintain mode_rx in spi_slave {}

Hence removed this code, and look for read command from normal
spi->mode from spi_slave{} and params->flags

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22 01:02:28 +05:30
Vignesh R
28b69f6488 spi: ti_qspi: Remove unnecessary udelay for AM437x
This udelay() was added as an HACK and is no longer required. All
read/write/erase operations work fine even without this delay. Hence,
remove the udelay() call.

Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22 00:58:26 +05:30
Vignesh R
260368507a spi: ti_qspi: use 128 bit transfer mode when writing to flash
TI QSPI has four 32 bit data registers which can be used to transfer 16
bytes of data at once. The register group QSPI_SPI_DATA_REG_3,
QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is
treated as a single 128-bit word for shifting data in and out. The bit
at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out
in case of 128 bit transfer mode. Therefore the first byte to be written
to flash should be at QSPI_SPI_DATA_REG_3[31-25] position.
Instead of writing 1 byte at a time when interacting with SPI NOR flash,
make use of all the four registers so that 16 bytes can be transferred
in one go.

With this patch, the flash write speed increases from ~250KBs/ to
~650KB/s on DRA74 EVM.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22 00:58:26 +05:30
Lad, Prabhakar
d2998286fc spi: zynq_spi: Fix infinite looping while xfer
During spi transfer, for example:
sspi 1:1.0 8 ff

the rx_len values will  be:
rx_len = 0
rx_len = 4294967295

This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo

Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-22 00:58:26 +05:30
Tom Rini
423620b9d4 Merge branch 'master' of git://git.denx.de/u-boot-mips 2016-09-21 14:50:18 -04:00
Tom Rini
f85fad024f Merge branch 'master' of http://git.denx.de/u-boot-mmc 2016-09-21 11:48:02 -04:00
Paul Burton
31d36f748c MIPS: Hang if run on a secondary CPU
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.

Prevent this from happening by simply hanging with an infinite loop if
we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
as appropriate, is non-zero.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 17:04:53 +02:00
Paul Burton
d263cda5ae MIPS: Fix cache maintenance in relocate_code & simplify
The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceeded to apply relocations & jump to the new code without flushing
the caches again. This is problematic as the instruction cache could
potentially have already fetched instructions that hadn't had relocs
applied.

Rework this to perform the flush_cache call using the code in the
original copy of U-Boot, after having applied relocations to the new
copy of U-Boot. The new U-Boot can then be jumped to safely once that
cache flush has been performed.

As part of this, since the old U-Boot is used up until after that cache
flush, complexity around loading values from the GOT using a jump & link
instruction & loads from a table is removed. Instead we can simply load
the needed values with PTR_LA fromt the original GOT.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 16:25:43 +02:00
Paul Burton
ad8783cb1c boston: Introduce support for the MIPS Boston development board
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 16:24:36 +02:00
Paul Burton
dd7c749474 clk: boston: Providea simple driver for Boston board clocks
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-21 15:04:32 +02:00