If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause
issues in future command reads. This issue came to light when some flash
reads in STIG mode were coming back dirty.
Co-developed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
OSPI controller supports all types of op variants in STIG mode,
only limitation being that the data payload should be less than
8 bytes when not using memory banks.
STIG mode is more stable for operations that send small data
payload and is more efficient than using DMA for few bytes of
memory accesses. It overcomes the limitation of minimum 4 bytes
read from flash into RAM seen in DAC mode.
Use STIG mode for all read and write operations that require
data input/output of less than 8 bytes from the flash, and thereby
support all four phases, cmd/address/dummy/data, through OSPI STIG.
Also, remove the reorder address chunk in apb_command_write since we now
setup ADDR BIT field that does the same job in a cleaner way.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
buswidth and dtr fields in spi_mem_op are only valid when the
corresponding spi_mem_op phase has a non-zero length. For example,
SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR
phase.
Fix the dtr checks in set_protocol() to ignore empty spi_mem_op
phases, as checking for dtr field in empty phase will result in
false negatives.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This patch adds fixups for s25fs512s to address the following issues
from reading SFDP:
- Non-uniform sectors by factory default. The setting needs to be
checked and assign erase hook as needed.
- Page size is wrongly advertised in SFDP.
- READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h)
are not supported.
- Bank Address Register (BAR) is not supported.
In addition, volatile version of Quad Enable is used for safety.
Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated
to use 4-byte address commands instead of extended address mode and the
page_size is fixed to 256
For future use, manufacturer code should be moved out from framework
code as same as in Linux.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
By the time we jump to the err label, count represents the number of
gpios we've successfully requested. So by subtracting one, we fail to
free the most recently requested.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Xen core_init() is calling HVC which should be called from EL1 level that's
why do Xen initialization only when U-Boot runs in EL1.
Signed-off-by: Michal Simek <michal.simek@amd.com>
U-Boot currently implements hypervisor calls only for ARM64 that's why add
dependency on ARM64. The hardware functionality is also available on
ARMv7a, but currently not supported by U-Boot, hence it is not added to the
list of dependencies here.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Since commit de39dc7162 ("arm: armv7-a: Compile and tune for armv7-a
instead of armv5") is used -march=armv7-a option for Omap3 platforms.
With directive ".arch_extension sec" it is possible for -march=armv7-a to
directly use ARM SMC instruction.
So enable ".arch_extension sec" in Omap3 lowlevel_init.S and replace hand
assembled ".word 0xe1600071" by "SMC #1".
Since commit 51d0638650 ("arm: omap-common: add secure smc entry") same
pattern is already used in arch/arm/cpu/armv7/omap-common/lowlevel_init.S.
Signed-off-by: Pali Rohár <pali@kernel.org>
Commit aeb40f1166 ("tools: env: use /run to store lockfile") updated the
path to the lockfile but did not update the documentation to match.
Use the new path in the documentation.
Fixes: aeb40f1166 ("tools: env: use /run to store lockfile")
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The non DM code path already would enable pci bus mastering. Do the
same for the DM code path.
Fixes AHCI problems I am seeing on an Intel Apollolake device.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[trini: Use ahci_dev not dev in the calls]
Signed-off-by: Tom Rini <trini@konsulko.com>
When building with clang, we see:
board/emulation/common/qemu_dfu.c:51:24: warning: 'memset' call operates on objects of type 'char' while the size is based on a different type 'char *' [-Wsizeof-pointer-memaccess]
As we're calling memset with the length set to the size of the pointer
and not the size of the buffer. Correct this with a call of the size of
the buffer itself.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
We can only use the old U-Boot API for standalone applications when
building U-Boot with GCC as it relies upon the "gd is a register" trick
that only GCC supports. Further, rework the rest of the options so that
they are in the API menu and only visible if API support is enabled.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add weak function psci_sysreset_get_status for platform to define
their own reset status with CONFIG_SYSRESET enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
XEN config can be enabled by other platforms (even it doesn't need to make
sense) that's why fix dependencies. XEN (xenbus.c) requires sscanf (also
pvblock needs it). And PVBLOCK is inside drivers/xen folder which requires
XEN to be enabled.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Sometimes when doing tests on real hardware we sometimes run in to the
case where some of these mounts haven't been fully flushed. Using the
--lazy option with umount will allow us to continue while letting the OS
handle flushing the data out still.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When building with clang, it notes that sdinfo may be unused
uninitialized in some cases. This appears to be true from reading the
code, and we can simply set the variable to zero to start with and be as
correct as before.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
When building with clang we get a warning that rdaddr could be
uninitialized in one case. While this cannot functionally happen, we can
easily silence the warning.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Toolchains which do not directly support using "isb" and "dsb" directly
are no longer functionally supported in U-Boot. Furthermore, clang has
for a long time warned about using the alternate form that we were.
Update the code.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When building for ARM64, we need to pass -ffixed-x18 and otherwise pass
-ffixed-r9. Rather than having this logic in two places, we can do this
once in arch/arm/config.mk. Further, while gcc will ignore being passed
both -ffixed-r9 and -ffixed-x18 and simply use -ffixed-x18, clang will
note that -ffixed-r9 is not used. Remove this duplication to also remove
the warning.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the case of using clang to build, and having not already enabled the
private libgcc, do not look for it, as it will not be found nor
required.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When we invoke $(CPP) to make u-boot.lds we have LDPPFLAGS available to
set other required flags here. As this file is for the target and not
the host, we must ensure that CPP knows what the target architecture is.
For this, pass in $(CLANG_TARGET).
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Today, only gcc has __builtin_aarch64_crc32b (clang-16 does not, for
example). Make this option depend on CC_IS_GCC.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The main configuration menu should not contain detail settings.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix dependencies
* Provide labels that are easier to grasp.
* Fix typo %s/whgch/which/
* Fix type %s/Is/is/
Fixes: 29784d62ed ("test: Add some tests for kconfig.h")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Default synchronous exceptions handler prints only esr and register
dump. Sometimes it requiers to see an address which caused exceptions
to understand what's going on
ARM ARM in section D13.2.41 states that FAR_EL2 will contain meanfull
value in case of ESR.EC holds 0x20, 0x21, 0x24, 0x25, 0x22, 0x34 or
0x35. Same applies for EL1.
This patch adds function whivh determine current EL, gets correct FAR
register and prints it on panic.
Signed-off-by: Pavel Skripkin <paskripkin@gmail.com>
The vexpress64 board family now relies on OF_CONTROL and
OF_HAS_PRIOR_STAGE, so platform-specific configuration requirements
are minimal.
The vexpress_aemv8a_semi_defconfig file defines many flags that are not
needed for a minimal boot, such as flash memory configuration.
Therefore create vexpress_fvp_defconfig which contains the minimum
configuration required to boot on an Arm v8a FVP.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
The Arm EBBR (Embedded Base Boot Requirements) require that the time
and basic networking EFI interfaces are available and working, so long
as the hardware has an RTC and network interface.
Arm FVPs typically have a memory-mapped PL031 RTC and a VIRTIO_NET
device defined in the device tree, so "imply" these in the Kconfig for
the FVP base model to simplify creating EBBR-compliant firmware.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
BASE_FVP now typically uses a devicetree provided by a prior boot stage
(typically Arm TF-A), so imply this option by default when
TARGET_VEXPRESS64_BASE_FVP is selected.
OF_HAS_PRIOR_STAGE selects OF_BOARD so this change is minor, but aligns
TARGET_VEXPRESS64_BASE_FVP with TARGET_VEXPRESS64_BASER_FVP.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Move to using .env file for setting up environment variables for am64x.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
If rev is equal to the array size, we'll access the array
one-past-the-end.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Bryan Brattlof <bb@ti.com>
u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does.
otherwise it will hang when enable mmu, that is what we encounter
in our SOC.
Signed-off-by: meitao <meitaogao@asrmicro.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 3bf38943ae
In order to make invalidation by VA more efficient, set the largest
block mapping to 2MB, mapping it onto level-2. This has no material
impact on u-boot's runtime performance, and allows a huge speedup
when cleaning the cache.
Signed-off-by: Marc Zyngier <maz@kernel.org>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 417a73581a
Some recent arm64 cores have a facility that allows the page
table walker to track the dirty state of a page. This makes it
really efficient to perform CMOs by VA as we only need to look
at dirty pages.
Signed-off-by: Marc Zyngier <maz@kernel.org>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 3c433724e6
To quote the author:
These patches will use bounce buffers when VIRTIO_F_IOMMU_PLATFORM
feature is in a virtio device.
This feature can be tested with qemu with -device virtio-iommu-pci. So
that when a -device virtio-blk-pci with iommu_platform=true, it will
uses the bounce buffer instead.
When building with clang, the compiler compains with
drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
else if (priv->mode & SPI_TX_OCTAL)
^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here
val |= ((bus_width >> 1) << BUS_WIDTH);
^~~~~~~~~
drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true
else if (priv->mode & SPI_TX_OCTAL)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning
So initialize bus_width to 1 and add a warning if none of the configured
modes matches
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
NPCM7xx/NPCM8xx default is boot from flash.
removed set clock feature due to reliability and security.
the clock will set by bootblock or tip.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The .supports_op() callback function returns true by default after
performing driver-specific checks. Therefore the driver cannot apply
the buswidth in devicetree.
Call spi_mem_default_supports_op() helper to handle the buswidth
in devicetree.
Fixes: 358f803ae2 ("spi: Add Socionext F_OSPI SPI flash controller driver")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
in spi_mem_dtr_supports_op we have a check for allowing only even number
of bytes to be r/w. Odd bytes writing can be a concern while writing
data to a flash for example because 8 DTR mode doesn't support it.
However, reading ODD Bytes even though may not be physically possible
we can still allow for it because it will not have serious implications
on any critical registers being overwritten since they are just reads.
Cc: Vaishnav Achath <vaishnav.a@ti.com>
Cc: Pratyush Yadav <pratyush@kernel.org>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Nikhil M Jain <n-jain1@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This should have been op->data.buswidth instead as we check for octal
bus width for the data related ops
Also add explanation for why there is checks for 8D even data bytes
Cc: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Pratyush Yadav <ptyadav@amazon.de>
Tested-by: Nikhil M Jain <n-jain1@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for CHIP_ERASE opcode 0xc7 . This is useful in case the
entire SPI NOR is supposed to be erase at once, as is it considerably
faster than 4k sector erase and even slightly faster than 64k block
erase. The spi_nor_erase_chip() implementation is adapted from Linux
6.1.y as of commit 7d54cb2c26dad ("Linux 6.1.14") . The chip erase is
only used in case the entire MTD device is being erased, and the chip
does support this functionality.
Timing figures from W25Q128JW:
16 MiB erase using 4kiB sector erase opcode 0x20 ... 107.5s
16 MiB erase using 64kiB block erase opcode 0xd8 ... 39.1s
16 MiB erase using chip erase opcode 0xc7 .......... 38.7s
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Devices advertising the VIRTIO_F_IOMMU_PLATFORM feature require
platform-specific handling to configure their DMA transactions.
When handling virtio descriptors for such a device, use bounce
buffers to ensure that the underlying buffers are always aligned
to and padded to PAGE_SIZE in preparation for platform specific
handling at page granularity.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: 1eff171e61
Reviewed-by: Simon Glass <sjg@chromium.org>
In preparation for bouncing virtio data for devices advertising the
VIRTIO_F_IOMMU_PLATFORM feature, allocate an array of bounce buffer
structures in the vring, one per descriptor.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: 3e052749e7
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the attach and detach logic for manipulating vring descriptors
out into their own functions so that we can later extend these to
bounce the data for devices with VIRTIO_F_IOMMU_PLATFORM set.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: f73258a4bf
Reviewed-by: Simon Glass <sjg@chromium.org>
In preparation for explicit bouncing of virtqueue pages for devices
advertising the VIRTIO_F_IOMMU_PLATFORM feature, introduce a couple
of wrappers around virtqueue allocation and freeing operations,
ensuring that buffers are handled in terms of page-size units.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: b4bb5227d4
Reviewed-by: Simon Glass <sjg@chromium.org>
