Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal
synchronous PCI clock. Knowledge about the currently configured
value might be helpful. So let's print it out upon bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:
AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.
Signed-off-by: Stefan Roese <sr@denx.de>
Till now only the ranges in the ebc node are updated with the values
currently configured in the PPC4xx EBC controller. With this patch now
the NOR flash size is updated in the device tree blob as well. This is
done by scanning the compatible nodes "cfi-flash" and "jedec-flash"
for the correct chip select number.
This size fixup is enabled for all AMCC eval board right now. Other
4xx boards may want to enable it as well, if this problem with multiple
NOR FLASH sizes exists.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
strcpy() was iused with the target address being a pointer to a
constant string, which potentially is read-only. Use a (writable)
array of characters instead.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
NULL is an absolute value and should not be relocated.
After this correction code like:
void weak_fun(void) __attribute__((weak));
printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:
0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec
Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>
This message is printed upon PCIe bus scan, not only upon error, but also
if no PCIe device is detected at all. Since this is not an error, let's
remove this message in this case. We already have the message
"link is not up." if there is no PCIe device present.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.
Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.
Signed-off-by: Stefan Roese <sr@denx.de>
u-boot reports a PCIE PLL lock error at boot time on Yucca board, and
left PCIe nonfunctional. This is fixed by making u-boot function
ppc4xx_init_pcie() to wait 300 uS after negating reset before the
first check of the PLL lock.
Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
All 4xx variants had their own, mostly identical get_OPB_freq()
function. Some variants even only had the OPB frequency calculated
in this routine and not supplied the sys_info.freqOPB variable
correctly (e.g. 405EZ). This resulted in incorrect OPB values passed
via the FDT to Linux.
This patch now removes all those copies and only uses one function
for all 4xx variants (except for IOP480 which doesn't have an OPB).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes the following compilation warning:
miiphy.c: In function 'emac4xx_miiphy_read':
miiphy.c:353: warning: dereferencing type-punned pointer will break
strict-aliasing rules
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces
the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct
in 4xx pci code.
When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register
setup can be overwritten through environment variables ptm1la, ptm1ms,
ptm2la and ptm2ms to do application specific pci target BAR configuration.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards. As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.
IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This patch adds a generic command for programming I2C bootstrap
eeproms on PPC4xx. An implementation for Canyonlands board is
included.
The command name is intentionally chosen not to be PPC4xx specific.
This way other CPU's/SoC's can implement a similar command under
the same name, perhaps with a different syntax.
Usage on Canyonlands:
=> chip_config
Available configurations (I2C address 0x52):
600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100
600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100
800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100
800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100
1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100
1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100
1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 ***
1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88
=> chip_config 600-nor
Using configuration:
600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100
done (dump via 'i2c md 52 0.1 10')
Reset the board for the changes to take effect
Other 4xx boards will be migrated to use this command soon
as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
In cpu/ppc4xx/speed.c initialization of sysInfo->freqOPB for 405EP was
left out for no obvious reason.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal"
booting on some 44x platforms. This breakage is only noticed in some
cases while powercycling. As it seems, the code in question in start.S
didn't invalidate TLB #0. This makes sense since this TLB is used for
the bootrom mapping. With the patch mentioned above even TLB #0 got
invalidated resulting in an error later on.
This patch now fixes this issue by only invalidating TLB #0 in the RAM-
booting case.
Tested succesfully on Sequoia and Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <Eibach@gdsys.de>
Current code only sets the PCI vendor id to 0x1014 and
leaved device id to 0x0000.
Ths patch ....
a) uses the correct PCI_VENDOR_ID_IBM macro for this
b) sets the default device ID as stated in the UM to 0x0156
by using PCI_DEVICE_ID_IBM_405GP for this.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some basic PCI initialisation from the 4xx cpu_init_f()
to cpu/ppc4xx/4xx_pci.c.
The original cpu_init_f() function enabled the 405EP's internal arbiter
in all situations. Also the HCE bit in cpc0_pci is always set.
The first is not really wanted for PCI adapter designs and the latter
is a general bug for PCI adapter U-Boots. Because it enables
PCI configuration by the system CPU even when the PCI configuration has
not been setup by the 405EP. The one and only correct place is
in pci_405gp_init() (see "Set HCE bit" comment).
So for compatibility reasons the arbiter is still enabled in any case,
but from weak pci_pre_init() so that it can be replaced by board specific
code.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch makes pll_write on PPC405EP boards
global and callable from C code.
pll_write can be used to dynamically modify the PLB:PCI divider
as it is required for 33/66 MHz pci adapters based on the 405EP.
board_early_init_f() is a good place to do that (check M66EN signal
and call pll_write() when it is required).
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch implements the is_pci_host() function in a similiar way
as it is used on 440 targets.
The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not
build on 405EP targets because checking the PCI arbiter is different.
So putting the fixed code into a separate function makes the code
more readable.
Also using is_pci_host() on 405 brings 405 and 440 PCI code
a little bit closer.
In preparation for an upcoming 405EP based PMC module I made this
function weak so that it can be overwritten from board specific code.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a debug compilation error for PPC4xx platforms, all
other architectures are not affected by this change. The 'handler'
pointer was undefined. The fix is exercised and has effect only if
DEBUG is defined.
Signed-off-by: Alessio Centazzo acpatin@yahoo.com
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes printf format string compilation warnings in several
debug statements. It also fixes the dump of DDR controller MQ registers
found on some 44x and 46x platforms. The current register dump code
uses incorrect DCRs to access these registers.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds another build target for the AMCC Sequoia PPC440EPx
eval board. This RAM-booting version is targeted for boards without
NOR FLASH (NAND booting) which need a possibility to initially
program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
configured to setup the SDRAM, this debugger can load this RAM-
booting image to the target address in SDRAM (in this case 0x1000000)
and start it there. Then U-Boot's standard NAND commands can be
used to program the NAND FLASH (e.g. "nand write ...").
Here the commands to load and start this image from the BDI2000:
440EPX>reset halt
440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
440EPX>go 0x1000000
Please note that this image automatically scans for an already
initialized SDRAM TLB (detected by EPN=0). This TLB will not be
cleared. This TLB doesn't need to be TLB #0, this RAM-booting
version will detect it and preserve it. So booting via BDI2000
will work and booting with a complete different TLB init via
U-Boot works as well.
Signed-off-by: Stefan Roese <sr@denx.de>
New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions
replace a number of architecture-specific implementations.
Also, providing default functions will allow all boards to enable
CONFIG_I2C_CMD_TREE. This was previously not possible since the
tree-form of the i2c command provides the ability to display and modify
the i2c bus speed which requires i2c_[set|get]_bus_speed() to be
present.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Many boards/controllers/drivers don't support an I2C slave interface,
however CONFIG_SYS_I2C_SLAVE is used in common code so provide a
default
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This patch now uses the correct ECC byte order (Smart Media - SMC)
to be used on the 4xx NAND FLASH driver. Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.
Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in
drivers/mtd/nand/nand_ecc.c for correct operation. This is done with
a seperate patch.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
__attribute__ follows gcc's documented syntax and is generally more
common than __attribute. This change is only asthetic and should not
affect functionality.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This additional text in the bootup log helps to see if the board is
configured for NAND-booting. Especially helpful for boards that can
boot from NOR and NAND (e.g. most of the AMCC eval boards).
Signed-off-by: Stefan Roese <sr@denx.de>
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC
addresses into the SoC registers instead.
Signed-off-by: Stefan Roese <sr@denx.de>
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.
The cpus that get converted here:
at91rm9200
mpc512x
mpc5xxx
mpc8260
mpc8xx
ppc4xx
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: John Rigby <jrigby@freescale.com>
CC: Stefan Roese <sr@denx.de>
PCI outbound address map configuration doesn't match the
PCI memory address range covered by appropriate TLB entry
configuration for canyonlands causing machine check
exceptions while accessing PCI memory regions. This patch
provides a fix for this issue.
Kazuaki Ichinohe observed and reported this issue while
testing display output with PCI ATI video card on canyonlands.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
