Commit graph

12 commits

Author SHA1 Message Date
Abhimanyu Saini
16dacb26a5 board: freescale: common: Add flag for LBMAP brdcfg reg offset
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:51 -07:00
Abhimanyu Saini
3faaa24b11 board: freescale: common: Conditionally compile IFC QXIS func
Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:50 -07:00
Gong Qianyu
98d9aa4013 freescale/qixis: Add support for booting from SD/QSPI
1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Scott Wood
548cf52fd5 freescale/qixis: Add support for booting from NAND
Use "qixis_reset nand" to reset the board to boot from NAND.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:51 -07:00
York Sun
c63e137014 powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Prabhakar Kushwaha
960aa89bda board/common: Add support for QIXIS read/write using i2c
QIXIS FPGA is accessable via both i2c and flash controller.
Only flash controller access is supported.

Add support of i2c based access. It is quite useful in the scenario
where either flash controller path is broken or not present.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Shaveta Leekha
c6cef92f63 powerpc/qixis: enable qixis dump command and add switch dumping command
Remove #ifdef so that "qixis dump" command is always available

Add "qixis_reset switch" command to dump switch settings
Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from
registers to figure out switch settings. Not all bits are available.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
Prabhakar Kushwaha
2ae4e8d958 board/freescale/common:Add support of QTAG register
QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE
fields. These fields have FPGA build version, image name and build date
information.

Add support to parse these fields to have complete FPGA image information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Shengzhou Liu
e4de13e38a powerpc/board: add present2 register definition for QIXIS
According to new QIXIS system definition, update QIXIS registers set
to add present2 register instead of obsolete ctl_sys2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
Prabhakar Kushwaha
9f26fd7947 board/freescale/common:QIXIS:Fix magic number usage
QIXIS FPGA layout defines the  address of registers but The actual register bit
implementation is board-specific,

So avoid use of magic numbers as it may vary across different boards's QIXIS
FPGA implementation.
Also, Avoid board specific defines in common/qixis.h

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:28 -05:00
Shengzhou Liu
ae6b03fefc powerpc/p3060qds: Add board related support for P3060QDS platform
The P3060QDS is a Freescale reference board for the six-core P3060 SOC.

P3060QDS Board Overview:
 Memory subsystem:
  - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
  - 128M Bytes NOR flash single-chip memory
  - 16M Bytes SPI flash
  - 8K Bytes AT24C64 I2C EEPROM for RCW
 Ethernet:
  - Eight Ethernet controllers (4x1G + 4x1G/2.5G)
  - Three VSC8641 PHYs on board (2xRGMII + 1xMII)
  - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
 PCIe: Two PCI Express 2.0 controllers/ports
 USB:  Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
 I2C:  Four I2C controllers
 UART: Supports two dUARTs up to 115200 bps for console
 RapidIO:  Two RapidIO, sRIO1 and sRIO2

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00