Commit graph

87 commits

Author SHA1 Message Date
Naga Sureshkumar Relli
aaf232f348 ARM64: zynqmp: Add cortexa53 edac node
This patch adds edac node for arm cortexa53 to report
errors on L1 and L2 caches.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Michal Simek
7418b7c6ea Revert "ARM64: zynqmp: Add serdes address space dp driver"
This reverts commit 786db82bd5.

Since we are using serdes driver , no need of mapping serdes register
space into DP driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Tested-by: Hyun Kwon <hyunk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Hyun Kwon
bfe279803f ARM64: zynqmp: drm: Add DMA index
Each plane can be associated with multiple DMA channels. So add
index for each DMA channel.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Michal Simek
9e826b6868 ARM64: zynqmp: Sync gpio node properties
Keep dtsi in sync with mainline kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Michal Simek
c0f277f306 ARM64: zynqmp: Remove xlnx,id property
Remove unused xlnx,id property because it is not the part of
DT binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Bharat Kumar Gogada
7d6ca73ab9 ARM64: zynqmp: pci: Updating device tree as per upstream
Updating required device tree changes as per mainlined driver
from 4.6 kernel.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Filip Drazic
a4d7d56037 ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domain
Previously, it was assumed that there is a 1:1 mapping between
PM ID defined in the platform firmware and a PM domain. However, there
can be a situation where multiple PM IDs belong to a single PM domain
(e.g. PM IDs for GPU and two pixel processors correspond to a single
PM domain).

This patch adds support for assigning more than one PM ID to
a single PM domain.

Updated documentation accordingly.

Assigned pixel processors PM IDs to GPU PM domain.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Filip Drazic
2af3932fca ARM64: zynqmp: DT: Add PM domains for GPU and PCIE
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Filip Drazic
7780a869d7 ARM64: zynqmp: DT: Remove unused PM domains for PLL
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Filip Drazic
c5e79ee74c ARM64: zynqmp: DT: Remove unused DDR PM domain
DDR power states are handled by the PM firmware, so this domain is
redundant. Also, since there is no device using this PM domain,
it will be powered off during boot, which is wrong.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:39 +01:00
Michal Simek
69d09dd74d ARM64: zynqmp: Add dcc port to dtsi
Add dcc to dtsi for supporting system without serial port.
DCC is enabled by default on ZynqMP.
Adding dcc to zcu100 and zcu102 which were tested.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:38 +01:00
Michal Simek
c926e6fbb6 ARM64: zynqmp: Remove DTC 1.4.2 warnings
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /amba has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name

This patch is fixing them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:38 +01:00
Michal Simek
c9811e14cf ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI
Add missing u-boot,dm-pre-reloc to get IPs initialized.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Alexander Graf
0a8c4f67f3 ARM64: zynqmp: Align gic ranges for 64k in device tree
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.

This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:01 +02:00
Michal Simek
85d1142eb6 ARM64: zynqmp: Use 64bit size cell format for memory node
Enable option to support more then 4GB memories in single size block.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
a84de48e75 ARM64: zynqmp: Fix DWC3 binding with the kernel
Use the same binding as is used in mainline Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
786db82bd5 ARM64: zynqmp: Add serdes address space dp driver
For run time serdes adjustment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
c588d15444 ARM64: zynqmp: Align register description
Separate register space and put it on more lines.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Hyun Kwon
939cfeafec ARM64: zynqmp: dp: Add default properties to zynqmp.dtsi
Add some default properties to zynqmp.dtsi.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Hyun Kwon
695d75a122 ARM64: zynqmp: Use correct addresses in node names
Reflect actual silicon addresses in DT node names.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
4e31d27b9c ARM64: zynqmp: Align node address with parent node for dpdma
Use right addresses for channel names

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
ca2f5878d6 ARM64: zynqmp: Add backward compatible string for uart
Mainline kernel has no r1p12 compatible string that's why console stops
to work with the latest DTS files. Append generic compatible string.
Keep in your mind that using this generic compatible string not all uart
features will be available.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
91a8b0ee69 ARM64: zynqmp: Fix coding style for pcie
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Bharat Kumar Gogada
33aec51742 ARM64: zynqmp: Extend pcie node to support legacy interrupts
Modifying device tree node to support legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
7c38ca36cb ARM64: zynqmp: Add interrupt-controller property to gpio nodes
GPIO driver supports an input interrupt that's why gpio node itself can
be labeled as interrupt controller.

Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Naga Sureshkumar Relli
908690098c ARM64: zynqmp: Add ddrc node in dts
This patch adds ddrc memory controller node in dts.
size mentioned in dts is 0x30000, because we need to access DDR_QOS
INTR registers located at fd090208 from this driver.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
VNSL Durga
b34d11de18 ARM64: zynqmp: Added clocks to DT
ZynqMP DMA's main clock and apb clock are added
in zynqmp DT.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
ff50d21bd2 ARM64: zynqmp: Add CCI-400 node
Add CCI-400 node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
Michal Simek
14cd9eabb8 ARM64: zynqmp: Add missing interrupt-parent to PMU node
ZynqMP is not using global interrupt-parent setting that's why
it has to be listed in every node separately. PMU node missed it and
this patch is adding it.

Reported-by: John Linn <John.Linn@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
Soren Brinkmann
8f4e3972a0 ARM64: zynqmp: DT: Add power domains
Add power-domains to the DT and attach devices to them.
The power-domains are all logical domains as understood by firmware.
Each PD is identified by a unique identifier that the platform firmware
understands.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
P L Sai Krishna
bd750e7a6c ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes
This patch adds broken-tuning property to SD and
eMMC nodes.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
Michal Simek
da2ad7843c ARM64: zynqmp: Sync GEM nodes with Linux
Remove jumbo properties which are handled in the driver directly
and use mainline compatible string which is already handled by the
driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
Edgar E. Iglesias
7f1d7d974b ARM64: zynqmp: Hook up the GEMs to the SMMU
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
Edgar E. Iglesias
88a85aac9f ARM64: zynqmp: Correct IRQ nr for the SMMU
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:03 +02:00
Soren Brinkmann
0d90e9d851 ARM64: zynqmp: DT: Fix UART compatible string
ZynqMP has r1p12 not r1p8. r1p12 contains break detection support.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Punnaiah Choudary Kalluri
d3fd433f07 ARM64: zynqmp: Correct the watchdog timer interrupt number
Corrected the watchdog timer interrupt number.
Origin value was for CSUPMU watchdog.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:56 +01:00
Michal Simek
44303dfa79 ARM: zynqmp: Add DTS for ep108 board
Add DTS for ep108 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
2015-11-04 14:49:51 +01:00