6 commits

Author	SHA1	Message	Date
Siew Chin Lim	3aef59f280	arm: socfpga: Move Stratix10 and Agilex clock manager common code ... Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>	2021-04-08 17:29:12 +08:00
Simon Glass	cd93d625fd	common: Drop linux/bitops.h from common header ... Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>	2020-05-18 21:19:23 -04:00
Ley Foon Tan	b9d1671829	arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset ... Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. Reported-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2020-04-27 09:14:52 +02:00
Ley Foon Tan	38229994af	arm: socfpga: Move Stratix10 and Agilex clock manager common code ... Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>	2020-01-07 14:38:33 +01:00
Ley Foon Tan	94172c7961	arm: socfpga: Convert clock manager from struct to defines ... Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>	2020-01-07 14:38:33 +01:00
Ley Foon Tan	508791a035	arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC ... Add Clock Manager driver support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2018-05-18 10:30:47 +02:00