Commit graph

542 commits

Author SHA1 Message Date
Tom Rini
166a77b34b - DHSOM update:
- Remove nWP GPIO hog
    - Increase SF bus frequency to 50Mhz and enable SFDP
    - Disable video output for DHSOM
    - Disable EFI
    - Enable DFU_MTD support
 - Create include file for STM32 gpio driver private data
 - Split board and SOC STM32MP15 configuration
 - Device tree alignement with v5.15-rc6 for STM32MP15
 - Add binman support for STM32MP15x
 - Normalise newlines for stm32prog
 - Update OTP shadow registers in SPL
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Merge tag 'u-boot-stm32-20211110' of https://source.denx.de/u-boot/custodians/u-boot-stm

- DHSOM update:
   - Remove nWP GPIO hog
   - Increase SF bus frequency to 50Mhz and enable SFDP
   - Disable video output for DHSOM
   - Disable EFI
   - Enable DFU_MTD support
- Create include file for STM32 gpio driver private data
- Split board and SOC STM32MP15 configuration
- Device tree alignement with v5.15-rc6 for STM32MP15
- Add binman support for STM32MP15x
- Normalise newlines for stm32prog
- Update OTP shadow registers in SPL
2021-11-10 14:11:30 -05:00
Patrick Delaunay
56a368f661 gpio: stm32: create include file for driver private data
The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.

This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10 17:03:36 +01:00
Minkyu Kang
2b77d9a3ee exynos78x0: pinctrl: set const to structs
to fix following checkpatch warings.
WARNING: struct  should normally be const

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-09 14:07:46 +09:00
Dzmitry Sankouski
69bde0410a SoC: exynos: add support for exynos 78x0
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets
introduced on March 2017.
Features:
- 8 Cortex A53 cores
- ARM Mali-T830 MP3 GPU
- LTE Cat. 7 (7880) or 6 (7870) modem

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Dzmitry Sankouski
d8428f73c3 pinctrl: exynos: add support for multiple pin banks
Iterate all pin banks to find a pin

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Bharat Gooty
fd921d2037 pinctrl: single: Add request() api
Add pinctrl_ops->request api to configure pctrl
pad register in gpio mode.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05 08:43:03 -04:00
Bharat Gooty
62f86c6a01 pinctrl: single: Parse gpio details from dt
Parse different gpio properties from dt as part of probe
function. This detail is required to enable pinctrl pad
later when gpio lines are requested.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2021-10-05 08:43:03 -04:00
Wolfgang Denk
0cf207ec01 WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 09:08:16 -04:00
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Simon Glass
9539738509 treewide: Use OF_REAL instead of !OF_PLATDATA
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
414cc15144 treewide: Simply conditions with the new OF_REAL
Use this new Kconfig to simplify the compilation conditions where
appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Yuan Fang
423e324de2 pinctrl: fix typo
fix typo in pinctrl Kconfig file to avoid git commit failure on
some commit hooks check.

Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
2021-09-14 09:07:18 -04:00
Ye Li
0bf4a77e1f pinctrl: Add pinctrl driver for imx8ulp
Add pinctrl driver for i.MX8ULP

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Simon Glass
0b1284eb52 global: Convert simple_strtoul() with decimal to dectoul()
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 13:32:14 -04:00
Marek Behún
5534fb4f48 arm64: a37xx: pinctrl: Correct PWM pins definitions
The PWM pins on North Bridge on Armada 37xx can be configured into PWM
or GPIO functions. When in PWM function, each pin can also be configured
to drive low on 0 and tri-state on 1 (LED mode).

The current definitions handle this by declaring two pin groups for each
pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"

This is semantically incorrect. The correct definition for each pin
should be one group with three functions: "pwm", "led" and "gpio".

Change the "pwmN" groups to support "led" function.

Remove "ledN_od" groups. This cannot break backwards compatibility with
older device trees: no device tree uses it since there is no PWM driver
for this SOC yet. Also "ledN_od" groups are not even documented.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-31 09:59:58 +02:00
Simon Glass
83061dbd1c Rename GPIO_SUPPORT to GPIO
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:29:36 -04:00
Simon Glass
4d159b6f84 pinctrl: Avoid coverity warning when checking width
The width is set up in single_of_to_plat() and can only have three values,
all of which result in a non-zero divisor. Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 331154)
2021-07-15 18:42:05 -04:00
Tom Rini
7e58a3a148 various minor sandbox improvements
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Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dm

various minor sandbox improvements
2021-07-07 13:34:42 -04:00
Tom Rini
5503435838 pinctrl: mscc: Fix multiple definition error
With gcc-11 we get a multiple errors here as the declarations for
mscc_pinctrl_ops and mscc_gpio_ops are missing an extern.

CC: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Lars Povlsen <lars.povlsen@microchip.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-07-07 10:17:54 -04:00
Patrick Delaunay
b953ec2bca dm: define LOG_CATEGORY for all uclass
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Marek Vasut
df8adad57d pinctrl: renesas: Import R8A779A0 V3U PFC tables
Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1
("Linux 5.12") . Add parts of PFC table integration from
pinctrl: renesas: Add R8A779A0 V3U PFC tables
by Hai Pham <hai.pham.ud@renesas.com>" .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:17 +02:00
Marek Vasut
a2a14854f2 pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.12
Synchronize R-Car Gen2/Gen3 pinctrl tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") . This is a rather large
commit, since the macros in sh-pfc.h also got updated, so
all the PFC tables must be updated in lockstep.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-07 19:35:22 +02:00
Vignesh Raghavendra
1e7879045f pinctrl: single: Fix probe failure getting register area size
If reg property of pinctrl-single node requires address translation then
probe fails with following message:

single-pinctrl pinctrl@4301c000: failed to get base register size

This is because driver uses dev_read_addr_size() to get size which also
tries to fetch untranslated addr and fails.
Fix this by using dev_read_addr_size_index() which takes care of address
translation and also makes following dev_read_addr() call redundant.

This fixes Ethernet failures on TI's AM654 based EVMs due to lack of
pinmux configuration.

Fixes: 9fd8a430f3 ("pinctrl: single: get register area size by device API")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-26 17:26:07 -04:00
Marek Behún
236f2ec432 treewide: Convert macro and uses of __section(foo) to __section("foo")
This commit does the same thing as Linux commit 33def8498fdd.

Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.

Remove the quote operator # from compiler_attributes.h __section macro.

Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24 14:21:30 -04:00
Marek Vasut
6fc323c1ae pinctrl: renesas: Implement unlock register masks
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.

To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.

This is a direct port of Linux 5.12 commit e127ef2ed0a6
("pinctrl: renesas: Implement unlock register masks") by
Ulrich Hecht <uli+renesas@fpond.eu>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21 15:00:17 +02:00
Marek Vasut
1fffcaefc1 pinctrl: renesas: Fix R-Car Gen2 help text
The help text for Gen2 entries had a copy paste error, still containing
the Gen3 string, while the description was correctly listing Gen2. Fix
the help text.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21 15:00:17 +02:00
Marek Vasut
c0de8e792b pinctrl: renesas: Deduplicate Kconfig
The help text in the Kconfig file was always a copy of the same thing.
Move single copy into the common PFC driver entry instead. Also fix a
copy-paste error in the PFC help text, which identified PFC as clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21 15:00:17 +02:00
Dario Binacchi
230bc623a4 pinctrl: single: fix a never true comparison
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero'
comparison of an unsigned value is never true.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-27 08:05:30 -04:00
Dario Binacchi
69414d86ed pinctrl: single: check function mask to be non-zero
Otherwise it can generate a division by zero, which has an undefined
behavior.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-27 08:05:30 -04:00
Tom Rini
2fbc804715 Merge tag 'ti-v2021.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Support for pinmux status command on beaglebone
- Updates for MMC speed modes for J721e-evm
- Fix MMC booting on omap35_logic_somlv board
2021-04-18 08:46:39 -04:00
Dario Binacchi
5532262d46 test: pinmux: add test for 'pinctrl-single' driver
The test adds two pinmux nodes to the device tree, one to test when a
register changes only one pin's mux (pinctrl-single,pins), and the other
to test when more than one pin's mux is changed (pinctrl-single,bits).
This required replacing the controller's register access functions when
the driver is used on sandbox.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
76d470de1a pinctrl: single: add get_pin_muxing operation
It allows to display the muxing of a given pin. Inspired by more recent
versions of the Linux driver, in addition to the address and the value
of the configuration register I added the pin function retrieved from
the DT. In doing so, the information displayed does not depend on the
platform, being a generic type driver, and it can be useful for debug
purposes.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
0b12162910 pinctrl: single: add get_pin_name operation
It returns the name of the requested pin.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
1dd7ae20de pinctrl: single: add get_pins_count operation
It returns the number of selectable pins.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
180531fc2f pinctrl: single: add register access functions
The configuration of pinmux registers was implemented with duplicate
code which can be removed by adding two functions for read/write access.
Access to 8-bit registers has also been added.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
d85b93e80b pinctrl: single: change function mask default value
The patch is inspired by more recent versions of the Linux driver.
Replacing the default value 0xffffffff of the function mask with 0 is
certainly more conservative in case the "pinctrl-single,function-mask"
DT property is missing.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
971c64a452 pinctrl: single: check "register-width" DT property
In more recent versions of the Linux kernel the driver's probe function
returns an error if the "pinctrl-single,register-width" DT property is
missing. The lack of this information, in fact, does not allow to know
whether to access the registers of the controller at 8, 16, ... bits.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Dario Binacchi
9fd8a430f3 pinctrl: single: get register area size by device API
Use dev_read_addr_size to get size of the controller's register area.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-12 11:17:15 +05:30
Dario Binacchi
fcf6a2b30a pinctrl: single: fix debug messages formatting
The dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val); prints the 'reg'
address preceded by the prefix 0x0x instead of 0x. This because the
printf '%pa' format specifier already prepends the prefix '0x' to the
address displayed.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-12 11:17:15 +05:30
Dario Binacchi
9b884e79a6 pinctrl: single: fix offset management
The pinmux configuration DT node of a peripheral does not define a
physical address but an offset. Only by adding it to the base address of
the controller it is possible to calculate the physical address of the
register to be configured. Printing an offset also requires a different
formatting option than a physical address.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-12 11:17:15 +05:30
Dario Binacchi
6719294694 pinctrl: single: fix the loop counter variable type
The 'n' variable is used as a loop counter, not as a physical address,
and is used in a comparison with an int. So it makes sense to change
its type from phys_addr_t to int.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-12 11:17:15 +05:30
Dario Binacchi
4ace4fa697 pinctrl: single: fix format of structure documentation
U-Boot adopted the kernel-doc annotation style.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-12 11:17:15 +05:30
Simon Glass
bddac45d04 pinctrl: Return -ENOSYS when system call is not available
Update the code to use -ENOSYS, which is the correct error code for an
unimplemented system call in U-Boot.

Also we should not check for a missing operations array as this is not
permitted. For now this can be covered by an assert().

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-04-06 16:33:19 +12:00
Tom Rini
7d23eb9260 First set of u-boot-atmel features for 2021.07 cycle
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Merge tag 'u-boot-atmel-2021.07-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for 2021.07 cycle:
This small feature set includes the implementation of the slew rate for
the PIO4 pin controller device, and a fix for arm926ejs-based
microprocessors that avoids a crash.
2021-03-30 11:24:09 -04:00
Weijie Gao
a449cdb881 pinctrl: mt7629: add jtag function and pin group
The EPHY LEDs of mt7629 can be used as JTAG. This patch adds the jtag pin
group to the pinctrl driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Weijie Gao
70a2b4220e pinctrl: mediatek: do not probe gpio driver if not enabled
The mtk pinctrl driver is a combination driver with support for both
pinctrl and gpio. When this driver is used in SPL, gpio support may not be
enabled, and this will result in a compilation error.

To fix this, macros are added to make sure gpio related code will only be
compiled when gpio support is enabled.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-03-20 16:24:27 -04:00
Sam Shih
e254d2c0a4 pinctrl: mediatek: add get_pin_muxing ops for mediatek pinctrl
This patch add get_pin_muxing support for mediatek pinctrl drivers

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2021-03-20 16:24:27 -04:00
Sam Shih
4fc5d4cedb pinctrl: mediatek: fix wrong assignment in mtk_get_pin_name
This is a bug fix for mtk pinctrl common part. Appearently pins should be
used instead of grps in mtk_get_pin_name().

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2021-03-20 16:24:27 -04:00
Lad Prabhakar
220f308a5c pinctrl: renesas: Add support for R8A774C0
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals.

This patch hooks R8A774C0 SoC with the pfc driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Lad Prabhakar
4ece226e80 pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11
Sync the R8A77990 SoC PFC tables with Linux 5.11 , commit f40ddce88593.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00