5 commits

Author	SHA1	Message	Date
Stefan Roese	cab99d6f32	ppc4xx: Fix compilation warning in denali_spd_ddr2.c ... Signed-off-by: Stefan Roese <sr@denx.de>	2008-04-29 14:44:54 +02:00
Stefan Roese	85ad184b3b	ppc4xx: Complete remove bogus dflush() ... Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr@denx.de>	2008-04-29 13:57:07 +02:00
Larry Johnson	eb14ebe813	ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup ... Signed-off-by: Larry Johnson <lrj@acm.org>	2008-03-31 12:20:59 +02:00
Larry Johnson	29e3500cbc	ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code ... Signed-off-by: Larry Johnson <lrj@acm.org>	2008-02-14 07:42:32 +01:00
Larry Johnson	aba19604d8	Add 440EPx DDR2 SPD DIMM support ... This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org>	2007-12-27 19:35:36 +01:00