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3 commits

Author SHA1 Message Date
Jagannadha Sutradharudu Teki
c91d0c74cf zynq: Enable CONFIG_DEFAULT_DEVICE_TREE 
Enabled default dts files on respective pre-board config
files this is way MAKEALL will works. and it's upto user
to build specific dts by specifying at build time.

$ make zynq_zc70x_config
$ make -->  with default dts zynq-zc702.dts
or
$ make DEVICE_TREE=zynq-zc702 --> Same configuration with zynq-zc706.dts

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 2014-01-10 15:18:33 +01:00
Jagannadha Sutradharudu Teki
86737bcf07 zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs 
CONFIG_SYS_SDRAM_SIZE is specific to a board hence moved
to specific pre-config board files.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 2014-01-10 15:18:33 +01:00
Jagannadha Sutradharudu Teki
796d49969e zynq: Add zynq zed board support 
Zed is a complete development board based on the
Xilinx Zynq-7000 All Programmable SoC.

APSOC:
- XC7Z020-CLG484-1
Memory:
- 512 MB DDR3
- 256 Mb Quad-SPI Flash(
- Full size SD/MMC card cage
Connectivity:
- 10/100/1000 Ethernet
- USB OTG (Device/Host/OTG)
- USB-UART
Expansion:
- FMC (Low Pin Count)
- Pmod. headers (2x6)
Video/Display:
- HDMI output (1080p60 + audio)
- VGA connector
- 128 x 32 OLED
- User LEDs (9)
User inputs:
- Slide switches (8)
- Push button switches (7)
Audio:
- 24-bit stereo audio CODEC
- Stereo line in/out
- Headphone
- Microphone input
Analog:
- Xilinx XADC header
- Supports 4 analog inputs
- 2 Differential / 4 Single-ended
Debug:
- On-board USB JTAG programming port
- ARM Debug Access Port (DAP)

For more info - http://zedboard.org/product/zedboard

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 2014-01-10 15:18:33 +01:00