Commit graph

24 commits

Author SHA1 Message Date
Trent Piepho
a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:25 -06:00
Anatolij Gustschin
dd332e18d0 85xx: socrates: fix DDR SDRAM tlb entry configuration
since commit be0bd8234b
tlb entry for socrates DDR SDRAM will be reconfigured
by setup_ddr_tlbs() from initdram() causing an
inconsistency with previously configured DDR SDRAM tlb
entry from tlb_table:

socrates>l2cam 7 9
IDX  PID      EPN  SIZE V TS           RPN U0-U3 WIMGE UUUSSS
  7 : 00 00000000 256MB V  0 -> 0_00000000  0000 -I-G- ---RWX
  8 : 00 00000000 256MB V  0 -> 0_00000000  0000 ----- ---RWX
  9 : 00 10000000 256MB V  0 -> 0_10000000  0000 ----- ---RWX

This patch makes the presence of the DDR SDRAM tlb entry in
the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
inconsistency.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:47:01 -06:00
Selvamuthukumar
9b827cf172 Align end of bss by 4 bytes
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-18 23:13:16 +01:00
Haiying Wang
dfb49108e4 Pass dimm parameters to populate populate controller options
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-18 21:54:04 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Anatolij Gustschin
d666b2d596 socrates: fix crash after relocation
Currently U-Boot crashes after relocation to RAM.
Changing the CPO value of the DDR SDRAM TIMING_CFG_2
register to READ_LAT + 1 (to the value it was before
conversion of socrates to new DDR code) fixes the
problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-09-22 21:48:07 +02:00
u-boot@bugs.denx.de
fb661ea444 85xx: socrates: autoprobe Lime chip
This patch is an attempt to implement autoprobing for the Lime
presence on the bus.
Configure GPCM for Lime CS2 and try to access chip ID registers.
Second read atempt delivers register values if the chip is present.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-09-13 02:07:39 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0e8d158664 rename CFG_ENV macros to CONFIG_ENV
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:06 +02:00
Anatolij Gustschin
e64987a892 85xx: socrates: Enable Lime support.
This patch adds Lime GDC support together with support for the PWM
backlight control through the w83782d chip.  The reset pin of the
latter is attached to GPIO, so we need to reset it in
early_board_init_r.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-09-09 10:14:13 +02:00
Detlev Zundel
3e79b588b5 85xx: Socrates: Major code update.
- Update the local bus ranges in the FDT for Linux for the various
  devices connected to the local bus via chip-select.

- Set the LCRR_DBYP bit in the LCRR for local bus frequencies
  lower than 66 MHz and uses I/O accessor functions consequently.

- UPM data update.

- Update of default environment and configuration.  Use I2C multibus
  as we do have two I2C buses.  Also enable sdram and ext2 commands.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2008-09-09 10:13:57 +02:00
Kumar Gala
be0bd8234b FSL DDR: Convert socrates to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:51 -05:00
Scott Wood
68cf19aae4 socrates: Update NAND driver to new API.
Also, fix some minor formatting issues, and simplify the handling of
"state" for writes.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-13 18:24:05 -05:00
Wolfgang Denk
c8a3b109f0 Cleanup out-or-tree building for some boards (.depend)
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-07-02 23:49:18 +02:00
Wolfgang Denk
e093a24762 Coding Style Cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-06-28 23:34:37 +02:00
Becky Bruce
9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Kumar Gala
859a86a25c 85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose.  This makes life
a bit easier going forward with the new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-11 01:52:23 -05:00
Sergei Poselenov
a23cddde1a Socrates: Added FPGA base address update in FDT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-06-11 00:30:34 -05:00
Sergei Poselenov
fd51b0e0e6 Socrates: NAND support added. Changed the U-Boot base address and
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-06-11 00:30:29 -05:00
Sergei Poselenov
31ca020861 Socrates: added missed file with UPMA configuration data.
Signed-of-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-06-11 00:30:14 -05:00
Sergei Poselenov
59abd15b43 Socrates: Added FPGA mapping. LAWs and TLBs cleanup.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-06-11 00:30:09 -05:00
Andy Fleming
e1eb0e25d9 socrates: Fix PCI clk fix patch
The submitted patch seems to have been more up-to-date, but an older patch was
already in the repository.  This patch encompasses the differences

Taken entirely from Sergei Poselenov <sposelenov@emcraft.com>

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-10 18:49:34 -05:00
Sergei Poselenov
5e1882df6a Socrates: Fix PCI bus frequency report
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-05-27 14:20:55 +02:00
Sergei Poselenov
e18575d5f5 socrates: changes to support FDT
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-20 23:27:49 +02:00
Sergei Poselenov
5d108ac8f4 Initial support for "Socrates" board
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-05-20 23:27:46 +02:00