Commit graph

13980 commits

Author SHA1 Message Date
Jagan Teki
f5871a66fd sunxi: Drop legacy usb_phy.c
Allwinner PHY USB code is now part of generic-phy framework,
so drop existing legacy handling like arch/arm/mach-sunxi.c
and related code areas.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Jagan Teki
dd3228170a usb: sunxi: Switch to use generic-phy
Allwinner USB PHY handling can be done through driver-model
generic-phy so add the generic-phy ops to relevant places
on host and musb sunxi driver and enable them in respective
SOC's.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Chen-Yu Tsai
fef73766d9 sunxi: clock: Fix OHCI clock gating for H3/H5
Clock gating bits on H43/H5 were wrong, fix them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Jagan Teki
26fc4d6c51 sunxi: clock: Fix clock gating for H3/H5/A64
clock gating bits on a64 are different than H3_H5, so fixed
only required bits on clock_sun6i.h.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Patrick Delaunay
7f7deb0c72 stm32mp1: use OTP to configure MAC address and serial number
Use OTP57 and 58 for MAC address
- OTP57 = MAC address  bits [31:0]
- OTP58 = MAC address  bit  [47:32] stored in OTP  LSB's

Use manufacture information in OTP13 to OTP15 to build unique
chip id saved in env variable "serial#"
(used for USB device enumeration)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
c3600e1f92 stm32mp1: add FUSE command support
Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
19f589923a stm32mp1: add bsec driver
Add a MISC driver with read and write access to BSEC IP
(Boot and Security and OTP control)
- offset 0: shadowed values
- offset 0x80000000: OTP fuse box values (SAFMEM)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
de20e43794 stm32mp1: remove the second TAMP_BOOT_CONTEXT update
The register TAMP_BOOT_CONTEXT is already updated in
get_bootmode() in cpu.c and no need to be done
twice.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
320d266368 stm32mp1: Allow to activate CONFIG_DEBUG_UART
Add the needed information to enable the debug uart
to have printf before the serial driver probe
(so before probe for clock, pincontrol and reset drivers)

To enable the debug on uart 4 (default console):
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_STM32=y

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Radoslaw Pietrzyk
246a5e5fc2 ram: stm32_sdram: Adds stm32f429-disco fixes for HardFault at booting
- adds reading FMC swap setting from DTB to SDRAM driver
- sets FMC swap for stm32f429-disco board
- changes ram start address to 0x90000000

Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:17 -04:00
Ramon Fried
9558ddab96 db410: added pinctrl node and serial bindings
Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26 18:19:16 -04:00
Ramon Fried
ad97051b7f mach-snapdragon: Introduce pinctrl driver
This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.

Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 18:19:16 -04:00
Ramon Fried
640dc34942 mach-snapdragon: Fix UART clock flow
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26 18:19:11 -04:00
Ramon Fried
ffada23ca7 db820c: set clk node to be probed before relocation
The clock and serial nodes are needed before relocation.
This patch ensures that the msm-serial driver will probe
and provide uart output before relocation.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Miquel Raynal
b91ad16a69 sandbox: dts: add Sandbox TPMv2.x node
This node declares the presence of the Sandbox TPMv2.x emulated chip,
available for testing.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:00 -04:00
Maxime Ripard
3def2f8dbb Revert "sunxi: binman: Add U-Boot binary size check"
This reverts commit 819f1e081c.

This check was introduced in order to cope with the size limitation we had
when we were still using the raw environment in MMC. However, this
introduces padding as well, which can result in an overly huge binary if
one wants to flash the environment to some other location.

Since we now have a FAT-based environment, this check is not so useful
anymore, so we can just drop it.

Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Måns Rullgård <mans@mansr.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-25 14:55:07 +05:30
Eugeniy Paltsev
429fa25e17 ARC: init debug uart in early common arc code
The debug UART is intended for use very early in U-Boot to debug
problems before serial drivers are up.

Call debug_uart_init right before board_init_f.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-05-24 15:59:17 +03:00
Heinrich Schuchardt
bd2a13f329 arm: print instructions pointed to by pc
If an exception occurs in a loaded image and the relocation offset is
unknown, it is helful to know the instructions pointed to by the
program counter. This patch adds the missing output.

A possible output is:
    Code: e1c560d0 e12fff1e e120077b e12fff1e (e7f7defb)

The parentheses indicate the instruction causing the exception.

The output can be disassembled using the decodecode script provided
by the Linux kernel project.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-05-23 22:06:41 -04:00
Michal Simek
d0f855f221 arm64: timer: Create timer_get_bootus for bootstage support
Implement timer_get_boot_us() based on available functions to support
bootstage command.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-23 22:06:41 -04:00
Tom Rini
ea37f0b312 arm: armv7m: Clean up some thumb / compiler flag options
- The correct way to build with thumb mode is to select SYS_THUMB_BUILD
- We should be setting -march=armv7-m in arch/arm/Makefile not the
  sub-config.mk file.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-23 13:03:42 -04:00
Tom Rini
f58e94602e at91: Minor tweaks to SPL logic for space savings on smartweb
- spl_board_init is empty on smartweb so drop that function
- When CONFIG_AT91SAM9_WATCHDOG is set we do not disable the watchdog in
  SPL and instead let full U-Boot handle it.  Instead of an empty
  function just do not call a function.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-22 22:08:57 -04:00
Masahiro Yamada
c3d3e2a1ef ARM: dts: uniphier: sync with Linux 4.17-rc6
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23 00:32:39 +09:00
Masahiro Yamada
8c09f1f4fc ARM: uniphier: rename environment variable fdt_file to fdtfile
For booting Linux in the generic distro mechanism, cmd/pxe.c
retrieves the FDT file name from "fdtfile" environment variable.

Rename "fdt_file" to "fdtfile" for easier migration to distro boot.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23 00:32:39 +09:00
Kunihiko Hayashi
f6acbf88e4 ARM: dts: uniphier: change phy-mode to 'internal' for LD11
Change the phy-mode property to 'internal' that means to use a built-in PHY
implemented on LD11 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23 00:32:39 +09:00
Kunihiko Hayashi
3c0fa6ce13 ARM: dts: uniphier: add clock-names and reset-names to ethernet node
Add clock-names and reset-names because this node recognizes multiple
clocks and resets.  ("ether", and so on, for each)

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23 00:32:39 +09:00
Kunihiko Hayashi
28cd3d2929 ARM: dts: uniphier: add required clocks and resets to Pro4 ethernet node
The GIO clock/reset, another MAC clock, and the PHY clock are required
for the ethernet of Pro4 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23 00:32:39 +09:00
Kunihiko Hayashi
69b3d4e930 ARM: dts: uniphier: add syscon-phy-mode property to each ethernet node
Add syscon-phy-mode property specifying a phandle of system controller
to each ethernet node.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-23 00:32:39 +09:00
Tom Rini
624d2cae34 SPDX: Fixup SPDX tags in a few new files
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-20 09:47:45 -04:00
Tom Rini
bea1649cd9 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-05-20 09:44:38 -04:00
Tom Rini
56932e84ea Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-05-20 09:44:13 -04:00
Tom Rini
904e546970 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-05-20 09:44:05 -04:00
Marek Vasut
232a1a5f8f ARM: rmobile: Unify Gen2 Makefile entry
Drop per-SoC Makefile entries and replace them with one unified entry
now that the PFC tables are gone. Shuffle the Makefile around a bit
to make it more organized.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Marek Vasut
5ec1fd8e93 ARM: rmobile: Drop old R8A7794 PFC tables
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Marek Vasut
a67a02d26d ARM: rmobile: Drop old R8A7793 PFC tables
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Marek Vasut
be0fc10c07 ARM: rmobile: Drop old R8A7792 PFC tables
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Marek Vasut
3bb2ff3426 ARM: rmobile: Drop old R8A7791 PFC tables
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Marek Vasut
70b5de78ea ARM: rmobile: Drop old R8A7790 PFC tables
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Marek Vasut
e9c891ff93 ARM: rmobile: Update V2H Blanche
The V2H Blanche port was broken since some time. This patch updates
the V2H Blanche port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-20 12:06:55 +02:00
Tom Rini
855ff8e6dd Fixup various SPDX tags from the latest merge
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-18 17:56:50 -04:00
Michal Simek
b4af64fdfd arm64: zynqmp: Use DWC3 generic driver and DM_USB
Remove harcoded XHCI lists and detect mode, speed based on DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Serial-changes: 2
- Remove also XHCI macros from hardware.h
- Remove additional new line in zcu106
2018-05-18 13:23:15 +02:00
Tom Rini
5f78786499 Merge git://git.denx.de/u-boot-imx 2018-05-18 07:11:11 -04:00
Ley Foon Tan
00f7ae6138 arm: dts: socfpga: stratix10: update dtsi and dts
Update dtsi and dts files for resets, phy node and other properties.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:48 +02:00
Ley Foon Tan
5fb033a336 arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:48 +02:00
Ley Foon Tan
73175d04a9 arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC
Add pinmux driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:48 +02:00
Ley Foon Tan
3607a8084a arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC
Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:47 +02:00
Ley Foon Tan
508791a035 arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC
Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:47 +02:00
Ley Foon Tan
641f7470b6 arm: socfpga: stratix10: Add watchdog and firewall base addresses
Add the base address for watchdog and firewall.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:47 +02:00
Ben Kalo
4916388a39 ARM: socfpga: Fix Documentation errors in scu_registers
According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers
Access Control register offset is 0x50.

Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2018-05-18 10:30:47 +02:00
Tien Fong Chee
011fa5f33d ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot
SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18 10:30:47 +02:00
Tien Fong Chee
c960ef29cd ARM: socfpga: Adding clock frequency info for U-Boot
Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18 10:30:47 +02:00
Tien Fong Chee
901af3e903 configs: Add DDR Kconfig support for Arria 10
This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:47 +02:00
Tien Fong Chee
5658a299bd ARM: socfpga: Add DDR driver for Arria 10
Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18 10:30:47 +02:00
Tien Fong Chee
53faef1e3f ARM: socfpga: Add DRAM bank size initialization function
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:47 +02:00
Tien Fong Chee
9ef9fe3455 ARM: socfpga: Rename the gen5 sdram driver to more specific name
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18 10:30:47 +02:00
Marek Vasut
32f99757f4 ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
6b49cdd27e ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff
Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest
Quartus to get the new set of clock bindings in.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
cc21ed62f9 ARM: socfpga: Synchronize Arria10 DTs
Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit
ef8216d28a5920022cddcb694d2d75bd1f0035ca

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
474315f563 ARM: socfpga: Sort the DT Makefile
Sort the Makefile entries, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
480f7f9c3e ARM: socfpga: Sync A10 clock manager binding parser
The A10 clock manager parsed DT bindings generated by Quartus the
bsp-editor to configure the A10 clocks. Sadly, those DT bindings
changed at some point. The clock manager patch used the old ones,
this patch replaces the bindings parser with one for the new set.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
73172753f4 ARM: socfpga: Convert to DM serial
Pull the serial port configuration from DT and use DM serial instead
of having the serial configuration in two places, DT and board config.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
48befc009f ARM: socfpga: Clean up Kconfig entries
Shuffle the default Kconfig entries around so it is not such a mess.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
f79173280c ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET
This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Lukasz Majewski
ee94365557 arm: imx53: Add support for imx53 boards from K+P
This commit adds support for DDC and HSC boards from
K+P in u-boot.

Console output:

U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200)

CPU:   Freescale i.MX53 rev2.1 at 800 MHz
Reset cause: WDOG
Model: K+P iMX53
DRAM:  512 MiB
MMC:   FSL_SDHC: 0
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Module EEPROM:
  ID: TQMa53-CB.0401
  SN: 63152762
  MAC: 00:0b:64:03:14:2a
BBoard:40x0 Rev:10
Net:   eth0: ethernet@63fec000
Hit any key to stop autoboot:  0

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-05-18 08:29:38 +02:00
Lukasz Majewski
686df498ef sandbox: Enable support for MC34708 PMIC in DTS
This commit also provides the default values of the emulated MC34708 PMIC
internal registers content.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18 08:27:26 +02:00
Jagan Teki
e810565e23 i.MX6DL: mamoj: Add PFUZE100 support
MX6DL Mamoj boards has Freescale PFUZE100 PMIC, add support
for it through DM_PMIC dt definition.

pmic log:
Reviewed-by: Stefano Babic <sbabic@denx.de>

========
=> pmic list
| Name                            | Parent name         | Parent uclass @ seq
| pfuze100@08                     | i2c@021f8000        | i2c @ 3
=> pmic dev pfuze100@08
dev: 0 @ pfuze100@08
=> pmic dump
Dump pmic: pfuze100@08 registers

0x00: 10 00 00 21 00 01 3f 01 00 7f 00 00 00 00 00 81
0x10: 00 00 3f 00 00 00 00 00 00 00 00 10 00 00 00 00
0x20: 2b 2b 2b 08 c4 00 00 00 00 00 00 00 00 00 2b 2b
0x30: 2b 08 c4 00 00 72 72 72 08 d4 00 00 2c 2c 2c 08
0x40: e4 00 00 2c 2c 2c 08 e4 00 00 6f 6f 6f 08 f4 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 48 00 00 00 10 06 1e 1e 17 10
0x70: 1a 1f 00 00 00 00 00 00 00 00 00 00 00 00 00

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
2018-05-18 08:23:43 +02:00
Jagan Teki
dda9892171 i.MX6DL: mamoj: Add I2C support
i.MX6DL Mamoj has i2c3 and i2c4 buses, add support
through DM_I2C with dt definition.

i2c log:
Reviewed-by: Stefano Babic <sbabic@denx.de>

=======
=> i2c bus
Bus 2:  i2c@021a8000
Bus 3:  i2c@021f8000
=> i2c dev 2
Setting bus to 2
=> i2c speed 400000
Setting bus speed to 400000 Hz
=> i2c probe
Valid chip addresses: 20 51 53
=> i2c md 53 0xff
00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
=> i2c md 51 0xff
00ff: a8 08 40 50 09 43 46 52 42 18 80 8e ae a9 d0 53    ..@P.CFRB......S
=> i2c dev 3
Setting bus to 3
=> i2c speed 100000
Setting bus speed to 100000 Hz
=> i2c probe
Valid chip addresses: 08 40 48 4B
=> i2c md 08 0xff
00ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
2018-05-18 08:23:43 +02:00
Jagan Teki
1494cc89cb i.MX6: board: Add BTicino i.MX6DL Mamoj initial support
Add initial support for i.MX6DL BTicino Mamoj board.

Mamoh board added:
- SPL
- SPL_DM
- SPL_OF_CONTROL
- DM for U-Boot proper
- OF_CONTROL for U-Boot proper
- eMMC
- FEC
- Boot from eMMC
- Boot from USB SDP

Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-18 08:23:43 +02:00
Jagan Teki
0f93f55c86 ARM: i.MX6: dts: Build dtb based on SOC type
Build dtb's based on SOC type instead building arch type.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-18 08:23:43 +02:00
Jagan Teki
9faa43c4b5 ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl
u-boot,dm-spl property is specific to U-Boot, so move it into
*u-boot.dtsi files for relevant i.MX6UL files.

This make syncing Linux dts files straight forward.

Also update the MAINTAINERS file for dts files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-18 08:23:43 +02:00
Jagan Teki
067a9daeb5 ARM: dts: imx6ul-isiot: Move usdhc2 into dtsi
Move usdhc2 node along with pinctrl to imx6ul-isiot.dts
from imx6ul-isiot-emmc.dts

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-18 08:23:43 +02:00
Jagan Teki
2175637843 ARM: dts: i.MX6QDL: U-Boot specific dts for u-boot, dm-spl
u-boot,dm-spl property is specific to U-Boot, so move it into
*u-boot.dtsi files for relevant i.MX6QDL files.

This make syncing Linux dts files straight forward.

Also update the MAINTAINERS file for dts files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-18 08:23:43 +02:00
Chris Packham
6a9f797623 ARM: kirkwood: Add device-tree for sheevaplug
Import the dts files from Linux 4.17 and enable device tree control in
u-boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:26 +02:00
Chris Packham
72f4013e95 ARM: kirkwood: Add device-tree for pogo_e02
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:26 +02:00
Chris Packham
e800ace560 ARM: kirkwood: Add device-tree for openrd
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
122b821189 ARM: kirkwood: Add device-tree for nas220
Import the dts file from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
519944e3c5 ARM: kirkwood: Add device-tree for iconnect
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
c8faf97e9a ARM: kirkwood: Add device-tree for ib62x0
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
3f023b2c81 ARM: kirkwood: Add device-tree for guruplug
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
0b28f86545 ARM: kirkwood: Add device-tree for goflexhome
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
f1f41dd770 ARM: kirkwood: Add device-tree for dockstar
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
07076ac5f3 ARM: kirkwood: Add device-tree for dns325
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Chris Packham
060c85d41c ARM: add devicetree files for kirkwood SoC
These files are taken verbatim from the Linux kernel 4.17

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-17 17:35:25 +02:00
Lukasz Majewski
768cce8b79 dts: pinctrl: Provide IMX_PAD_SION definition for imx53 pinctrl
The SION pin must be set for proper operation of I2C when DM is enabled.

When legacy I2C is used, this bit is set implicitly in the u-boot code:
arch/arm/include/asm/arch-mx5/iomux-mx53.h:92:
MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 |
	IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),

The Linux kernel uses similar approach with:
arch/arm/boot/dts/imx53-tqma53.dtsi:182:
	MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000

After applying this patch it is possible to have the I2C working with DM
on imx53 devices:

MX53_PAD_KEY_ROW3__I2C2_SDA (0x1ee | IMX_PAD_SION)

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-05-17 12:13:00 +02:00
Lukasz Majewski
0a107afde6 dts: imx53: Add gpio and i2c nodes to imx53.dtsi file
Those DTS nodes has been ported from Linux kernel (v4.16)

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-05-17 12:12:45 +02:00
Peter Robinson
02ada2d958 mx6: Select CONFIG_MP with MX6_SMP
It makes sense to select the MP multi processor option at the same time we
select the other SMP options needed for SMP capable i.MX6 SoCs.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2018-05-17 12:04:22 +02:00
Magnus Lilja
71720d6793 mx31: Convert MX31_HCLK_FREQ and MX31_CLK32 to Kconfig.
Also remove the #ifdef's from clock.h since the Kconfig values defaults
the to old default values in clock.h.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-17 12:02:28 +02:00
Magnus Lilja
3159ec64f5 mx31pdk: Convert CONFIG_MX31 flag to use Kconfig.
Move CONFIG_MX31 from mx31pdk.h to mx31pdk_defconfig and introduce
necessary Kconfig changes as well.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-17 12:02:24 +02:00
Ian Ray
51a42bea52 board: ge: bx50v3: remove redundant targets
This replaces TARGET_GE_B{4,6,8}50V3 with common TARGET_GE_BX50V3.
The boards are identified automatically at runtime.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
2018-05-17 11:58:48 +02:00
Patrice Chotard
9938e068fa ARM: dts: stm32: Update qspi bindings for stm32f746
Align qspi bindings following kernel dt-bindings
Documentation/devicetree/bindings/mtd/stm32-quadspi.txt
from kernel v4.17-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Patrice Chotard
9582100eee ARM: dts: stm32: Add quadspi reset for stm32f746
Add missing reset property in quadspi node.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-16 18:41:21 +05:30
Jaehoon Chung
105e3d84e5 ARM: dts: exynos5: add the interrupt-parent property
Add the interrupt-parent property as gic.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-05-16 11:25:12 +09:00
Jaehoon Chung
631bacefb3 ARM: dts: exynos5: remove the duplicated nodes
Remove the duplicated gic and combiner nodes in exynos5.dtsi.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-05-16 11:25:12 +09:00
Bryan O'Donoghue
73171c8d53 nds32: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
nds2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nds32 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
76b916f233 nds32: Define PLATFORM__SET_BIT for generic_set_bit()
nds32 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in nds32
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
ff83066cc7 nios2: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
nios2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nios2 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
7ed4370bb9 nios2: Define PLATFORM__SET_BIT for generic_set_bit()
nios2 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in nios2
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
accdce5f86 riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
820cba2ce8 riscv: Define PLATFORM__SET_BIT for generic_set_bit()
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-15 21:44:05 -04:00
Bryan O'Donoghue
30fe8b05b3 x86: Define PLATFORM__SET_BIT for generic_set_bit()
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2018-05-15 21:44:05 -04:00
Tom Rini
c75990889d Merge branch 'master' of git://git.denx.de/u-boot-video 2018-05-15 08:29:24 -04:00
Vasily Khoruzhick
3ecec5aadd dts: sunxi: add PWM node for sun50i
Add PWM definition to sun50i-a64.dtsi

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15 08:18:14 +02:00
Vasily Khoruzhick
1c353aea2b pwm: sunxi: add support for PWM found on Allwinner A64
This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15 08:18:09 +02:00
Chris Packham
ed52ea507f net: add Kconfig for MVGBE
Add Kconfig for MVGBE and update boards to select this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-05-14 21:28:38 -04:00
Chris Packham
c4195d5553 ARM: mvebu: a38x: move sys_env_device_rev_get
Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Chris Packham
e6fce12d14 ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:01:56 +02:00
Marek Behún
80af1a9ef6 arm64: mvebu: Add basic support for the Turris Mox board
This adds basic support for the Turris Mox board from CZ.NIC, which is
currently being crowdfunded on Indiegogo.

Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).

The basic module can be extended by different modules. The device tree
binary for the kernel can be dependent on which modules are connected,
and in what order. Because of this, the board specific code creates
in U-Boot a variable called module_topology, which carries this
information.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Marek Behún
2b69a67389 watchdog: Add support for Armada 37xx CPU watchdog
This adds support for the CPU watchdog found on Marvell Armada 37xx
SoCs.

There are 4 counters which can be set as CPU watchdog counters.
This driver uses the second counter (ID 1, counting from 0)
(Marvell's Linux also uses second counter by default).
In the future it could be adapted to use other counters, with
definition in the device tree.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Marek Behún
dbbd5bdd27 spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency
Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.

Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Marek Behún
82a248df9a driver: clk: Add support for clocks on Armada 37xx
The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
  - since setting rate is not supported, the driver computes the rates
    when probing and so subsequent calls to the .get_rate method do not
    read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

  - the .set_parent method theoretically could be supported on some clocks
    (the parent would have to be one of the TBG clocks)

  - the .set_rate method would have to try all the divider values to find
    the best approximation of a given rate, and it doesn't seem like
    this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Marek Behún
22f418935b phy: marvell: a3700: Use comphy_mux on Armada 37xx.
Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.

This is needed for Armada 37xx.

This introduces new device tree bindings. AFAIK there is currently no
driver for Armada 37xx comphy in Linux. When such a driver will be
pushed into Linux, this will need to be rewritten accordingly.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14 10:00:15 +02:00
Tom Rini
9a66328a37 Merge git://git.denx.de/u-boot-tegra 2018-05-11 15:22:36 -04:00
Tom Rini
3b52847a45 Xilinx changes for v2018.07
microblaze:
 - Align defconfig
 
 zynq:
 - Rework fpga initialization and cpuinfo handling
 
 zynqmp:
 - Add ZynqMP R5 support
 - Wire and enable watchdog on zcu100-revC
 - Setup MMU map for DDR at run time
 - Show board info based on DT and cleanup IDENT_STRING
 
 zynqmp tools:
 - Add read partition support
 - Add initial support for Xilinx bif format for boot.bin generation
 
 mmc:
 - Fix get_timer usage on 64bit cpus
 - Add support for SD3.0 UHS mode
 
 nand-zynq:
 - Add support for 16bit buswidth
 - Use address cycles from onfi params
 
 scsi:
 - convert ceva sata to UCLASS_AHCI
 
 timer:
 - Add Cadence TTC for ZynqMP r5
 
 watchdog:
 - Minor cadence driver cleanup
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlr1ldMACgkQykllyylKDCHioACghoJw6+NqsZXl8zGWRP38yZ5K
 mvgAnihfOQq125mpKPZmcc5yt6wVwYIU
 =8ji9
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup
2018-05-11 11:45:28 -04:00
Tom Rini
c590e62d3b Merge git://git.denx.de/u-boot-fsl-qoriq 2018-05-11 07:09:21 -04:00
Michal Simek
1d6c54ecb3 arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5>

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:23 +02:00
Nitin Jain
0678941ae5 arm64: zynqmp: Setup MMU map for DDR at run time
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.

The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.

Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
767afebbcd arm64: zynqmp: Enable cadence WDT for zcu100
Enable watchdog on zcu100 to make sure if there is a bug in the u-boot
there is proper reset.
Watchdog expires and PMU fw is informed and based on setting proper
action is taken.

The patch is enabling reset-on-timeout feature and also fixing fixed
clock rate for watchdog where 100MHz is max (and also default) clock value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Siva Durga Prasad Paladugu
04ab29ab25 arm64: zynqmp: Add new defconfig for zc1275 revB
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
0b4b82ad14 arm: zynq: Remove checkboard and enable DISPLAY_CPUINFO
Now that showing silicon version is part of the CPU
info display, let's remove checkboard().

Note that the generic show_board_info() will still
show the DT 'model' property. For instance:

U-Boot 2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200)

CPU:   Zynq 7z045
Silicon: v1.0
Model: Zynq ZC706 Development Board
I2C:   ready

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>,
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

mini configuration doesn't need to show this information.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
4aba5fb857 arm: zynq: Rework FPGA initialization
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
57213c5f37 arm: zynq: Enable debug_uart_init in spl when enabled
In past this code was commented and was used for debug purpose.
But there is no reason not to enabled it based on macros.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Tom Rini
3aba3fd654 Merge git://git.denx.de/u-boot-socfpga 2018-05-10 22:57:41 -04:00
Tom Rini
f739fcd831 SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed.  These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict.  This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.

Fixes: 83d290c56f ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-10 20:38:35 -04:00
Hannes Schmelzer
7f1cb1d588 bootm: fix 'memory-fixup' for vxWorks boot
The check for having a memory node within the fdt blob is made wrong, we
fix this here.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2018-05-10 20:38:34 -04:00
Marcel Ziswiler
6ab8a2b0ee apalis_t30: describe pcie ports
Add some more comments describing the various PCIe ports available.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:30 -07:00
Marcel Ziswiler
c0cb8c8e86 apalis-tk1: add missing as3722 gpio0 configuration
As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module
explicitly configure it to high-impedance as well.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-10 16:34:20 -07:00
Tom Rini
e8f80a5a58 Merge git://git.denx.de/u-boot-sunxi 2018-05-09 12:58:06 -04:00
Hou Zhiqiang
8b40f22900 armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robust
Mask HRESET_B after cleared the the RCW_SRC, because in the workaround
we override the RCW_SRC and if HRESET_B is issued after the override
then SoC cannot find valid RCW as the RCW_SRC was overwritten and
result in hang. So we need to mask HRESET_B in case user asserts it,
and the PORESET_B should be asserted which leads to resampling of
cfg_rcw_src pins and loading of correct RCW_SRC.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Hou Zhiqiang
945fad57be armv8/fsl-lsch2: correct QMAN clock
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Sumit Garg
8044900a5b armv8: sec_firmware: Add support for multiple loadables
Enable support for multiple loadable images in SEC firmware FIT image.
Also add example "sec_firmware_ppa.its" file.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Takuma Ueba
6a265aba30 powerpc: mpc85xx: Improve Work-around for Erratum A005125
Work-around for Erratum A005125 must be applied to all cores.

Signed-off-by: Yoshihisa Morizumi <yoshi.morizumi@jp.fujitsu.com>
Signed-off-by: Takuma Ueba <ueba.takuma@jp.fujitsu.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Ruchika Gupta
b6bb93de75 armv8: sec_firmware: Remove JR3 from device tree node in all cases
JR3 was getting removed from device tree only if random number
generation was successful. However, if SEC firmware is present,
JR3 should be removed from device tree node irrespective of the
random seed generation as SEC firmware reserves it for it's use.
Not removing it in case of random number generation failure causes
the kernel to crash.

Random number generation was being called twice. This is not
required. If SEC firmware is running, SIP call can be made to the SEC
firmware to get the random number. This call itself would return
failure if function is not supported. Duplicate calling of random
number generation function has been removed.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Sriram Dash
bda33d3c6c armv8: layerscape: Avoid code duplication for TZASC Instantiation
TZASC controller configurations are similar. Put them in a macro and
avoid code duplication.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-05-09 09:17:51 -05:00
Grygorii Strashko
218ac107c5 arm: bitops: fix find_next_zero_bit() for case size < 32
find_next_zero_bit() incorrectly handles cases when:
- total bitmap size < 32
- rest of bits to process

static inline int find_next_zero_bit(void *addr, int size, int offset)
{
	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
	unsigned long result = offset & ~31UL;
	unsigned long tmp;

	if (offset >= size)
		return size;
	size -= result;
	offset &= 31UL;
	if (offset) {
		tmp = *(p++);
		tmp |= ~0UL >> (32-offset);
		if (size < 32)
[1]
			goto found_first;
		if (~tmp)
			goto found_middle;
		size -= 32;
		result += 32;
	}
	while (size & ~31UL) {
		tmp = *(p++);
		if (~tmp)
			goto found_middle;
		result += 32;
		size -= 32;
	}
[2]
	if (!size)
		return result;
	tmp = *p;

found_first:
[3]  tmp |= ~0UL >> size;

^^^ algo can reach above line from from points:
 [1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1
 [2] size < 32 - rest of bits to process
 in both cases bits to search are tmp[size-1..0], but line [3] will simply
 set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail.

example: bitmap size = 16, offset = 0, bitmap is empty.
 code will go through the point [2], tmp = 0x0
 after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16.

found_middle:
	return result + ffz(tmp);
}

Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3].

Fixes: 81e9fe5a29 ("arm: implement find_next_zero_bit function")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-05-08 18:50:23 -04:00
Ramon Fried
707e6ef964 db410c: set clk node to be probed before relocation
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.

Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
2018-05-08 18:50:22 -04:00
Patrice Chotard
da33b0a1ca ARM: dts: sti: Add stih410-b2260-u-boot.dtsi
STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs.
As currently no U-boot driver is available for the USB3 PHY and to avoid
issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY
using stih410-b2260-u-boot.dtsi file.

Fixes: 2fd4242cc5 ("ubs: xhci-dwc3: Enable USB3 PHY when available")

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 18:50:22 -04:00
Marek Vasut
34fc2a6edf ARM: socfpga: Add boot trampoline for Arria10
The Arria10 uses slightly different boot image header than the Gen5 SoCs,
in particular the header itself contains an offset from the start of the
header to which the Arria10 jumps. This offset must not be negative, yet
the header is placed at offset 0x40 of the bootable binary. Therefore, to
jump into U-Boot, add a trampoline just past the Arria10 boot header and
point to this trampoline at fixed offset from the header generated using
the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump back
to offset 0x0 of the image, it is possible to jump directly at the reset
label and save processing two instructions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
2018-05-08 21:08:42 +02:00
Patrice Chotard
dbe2fcb87d ARM: dts: stm32mp157: Add vrefbuf DT node
Add vrefbuf device tree node. This allows to get
a voltage reference for ADCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:40 -04:00
Patrice Chotard
21299d3a68 ARM: dts: stm32mp157c-ed1: Add regulator node
Add regulator nodes needed by stpmu1 regulator driver
Add vmmc-supply and vqmmc-supply regulator property for
sdmmc1 and sdmmc2.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:39 -04:00
Patrice Chotard
7c339bbae6 ARM: dts: stm32mp157: Add SoC pwr regulator entry
Add SoC power regulator entry for reg11, reg18 and usb33
regulator.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:38 -04:00
Patrick Delaunay
e8b85e810a stm32mp: regulator: add SoC pwr regulator support
This driver binds and manages the following regulator of
SoC's PWR block :
  - reg11
  - reg18
  - usb33

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-08 09:07:38 -04:00
Mario Six
cb61c9ec64 arm: controlcenterdc: Add spi-flash compatible strings
Since kirkwook SPI was recently converted to DM, add compatible strings
to the SPI flash devices to make them work with the new driver.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-05-08 09:07:37 -04:00
Praneeth Bajjuri
cd30f3fc9e arm: dra76: fastboot: extend cpu type for getvar command
'commit dda0bd674481 ("arm: dra762: Add support for device package identification")'
introduces ABZ and ACD package identification.

This patch is to extend usage of "fastboot getvar cpu" for
DRA76x ABZ and ACD devices.

Helps in fixing the boot warning.

Warning: fastboot.cpu: unknown CPU rev: 123863298
on
CPU  : DRA762-GP ES1.0 ABZ package
Model: TI AM5748 IDK
Board: AM574x IDK REV 1.0A

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-08 09:07:37 -04:00
Ludovic Desroches
8ee54672df gpio: atmel_pio4: give a full configuration when muxing pins
When a pin is muxed to a peripheral or as a GPIO, the only
configuration that can be set is the pullup. It is too restrictive
so this patch allows to give a full configuration.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-05-08 09:07:36 -04:00
Ludovic Desroches
cbccb33584 gpio: atmel_pio4: add drive strength macros
Macros for drive strength configuration were missing.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2018-05-08 09:07:35 -04:00
Neil Armstrong
7d750c3520 ARM64: meson: Sync DT and Bindings with Linux 4.16
Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.16.0.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-05-08 09:07:34 -04:00
Neil Armstrong
f0f3762cb7 ARM: meson: rename GXBB to GX
Taking into account the Amlogic Family name starts with GX, including
the GXBB, GXL and GXM SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-05-08 09:07:34 -04:00
Patrick Bruenn
274fb461f4 dm: led: add testcase for "default-state" property
Add two more gpio-leds to sandbox test device tree with default-state
property set to "on"/"off".
Add dm_test_led_default_state() to check that these new LED's are set to
LEDST_ON and LEDST_OFF.

dm: led: add testcase for "default-state" property

Add two more gpio-leds to sandbox test device tree with default-state
property set to "on"/"off".
Add dm_test_led_default_state() to check that these new LED's are set to
LEDST_ON and LEDST_OFF.

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2018-05-08 09:07:33 -04:00
Lokesh Vutla
a43d46a73c arm: v7R: Add support for enabling caches
Cache maintenance procedure is same for v7A and v7R
processors. So re-use cache-cp15.c file except for
mmu parts.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-07 15:53:29 -04:00
Lokesh Vutla
f2ef204312 arm: v7R: Add support for MPU
The Memory Protection Unit(MPU) allows to partition memory into regions
and set individual protection attributes for each region. In absence
of MPU a default map[1] will take effect. Add support for configuring
MPU on Cortex-R, by reusing the existing support for Cortex-M processor.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-07 15:53:29 -04:00
Michal Simek
4bbd6b1d94 arm: v7R: Add initial support
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded,
real-time systems. It implements the ARMv7-R architecture, and includes
Thumb-2 technology for optimum code density and processing throughput.

Except for MPU(Memory Protection Unit) and few CP15 registers, most of the
features are compatible with v7 architecture. So,reuse the same armv7
folder and introduce a new config CPU_V7R in order to differentiate
from v7 based platforms.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:28 -04:00
Lokesh Vutla
f4bcd767bd arm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15
Certain ARM architectures like ARMv7-A, ARMv7-R has support for
enabling caches using CP15 registers. To have a common support
for all these architectures, introduce a Kconfig symbol
SYS_ARM_CACHE_CP15 that selects cache-cp15.c

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:28 -04:00
Lokesh Vutla
7240b80ee0 arm: v7: Kconfig: Add entry for MMU
Add a Kconfig entry for MMU and imply for all platforms using
cache-cp15.c containing MMU setup. Using imply instead of select so that
MMU can be disabled by defconfigs when not needed.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:28 -04:00
Lokesh Vutla
acf1500138 arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:24 -04:00
Lokesh Vutla
2a5180535c arm: v7: Update VBAR only if available
Not all ARM V7 based cpus has VBAR for remapping
vector base address. So, update VBAR only if it available.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:49:52 -04:00
Masahiro Yamada
99552c3435 test: regmap: test Linux-compatible syscon_node_to_regmap()
Like Linux, syscon_node_to_regmap() allows a node to work as a syscon
provider without binding it to a syscon driver.  Test this.

Requested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-07 15:49:52 -04:00
Masahiro Yamada
d35812368a regmap: change regmap_init_mem() to take ofnode instead udevice
Currently, regmap_init_mem() takes a udevice. This requires the node
has already been associated with a device. It prevents syscon/regmap
from behaving like those in Linux.

Change the first argumenet to take a device node.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-07 15:49:51 -04:00
Masahiro Yamada
8c1de5e08b regmap: clean up regmap allocation
Putting zero length array at the end of struct is a common technique
to embed arbitrary length of members.  There is no good reason to let
regmap_alloc_count() branch by "if (count <= 1)".

As far as I understood the code, regmap->base is an alias of
regmap->ranges[0].start, but it is not helpful but make the code
just ugly.

Rename regmap_alloc_count() to regmap_alloc() because the _count
suffix seems pointless.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: fixup cpu_info-rcar.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 15:15:27 -04:00
Patrick Delaunay
9ce751a6f5 psci: arm: remove armv7 function psci_save_target_pc
This function is no more used, and replaced by psci_save
which save also context id as requested by PSCI requirements.

Even if the context id is not used by Linux, it should be saved
and restored in r0 when the CPU_ON is performed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07 11:52:55 -04:00
Patrick Delaunay
9622c7e65d sunxi: psci: save context id in cpu_on command
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07 11:52:55 -04:00
Patrick Delaunay
4f7dc2e603 uniphier: psci: save context id in cpu_on command
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-07 11:52:55 -04:00
Patrick Delaunay
4c6fe075ce tegra: psci: save context id in cpu_on command
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2018-05-07 11:52:55 -04:00
Patrick Delaunay
47ec6b4ea3 imx7: psci: save context id in cpu_on command
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07 11:52:55 -04:00
Patrick Delaunay
60599c1c08 ls102xa: psci: save context id in cpu_on command
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07 11:52:54 -04:00
Patrick Delaunay
41c79775f0 arm: stm32mp1: add PSCI support
Add PSCI v1.0 support for Linux and manage PSCI state
for each CPU (affinity 0 level) with all mandatory functions:
- PSCI_VERSION
- CPU_SUSPEND
- CPU_OFF
- CPU_ON
- AFFINITY_INFO
- SYSTEM_OFF
- SYSTEM_RESET
- PSCI_FEATURES
and 1 optional to avoid Linux warning
- MIGRATE_INFO_TYPE

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
2018-05-07 11:52:48 -04:00
Patrick Delaunay
486daaa618 arm: psci: add a weak function psci_arch_cpu_entry
The added function psci_arch_cpu_entry() is called
during psci_cpu_entry() and can be used by arch to handle
PSCI state transition from ON_PENDING to ON.

The default weak function is empty: not behavior change.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07 11:45:15 -04:00
Patrick Delaunay
1a047c23f9 arm: psci: save context id for cpu_on PSCI command
Save and use the 3rd parameter of PSCI CPU_ON request: context_id.

The context_id parameter is only meaningful to the caller.
U-Boot PSCI preserves a copy of the value passed in this parameter.
Following wakeup from a  powerdown state, U-BOOT PSCI places
this value in R0 when it first enters the OS.

NB: this context id is not (yet?) used by Linux but it is mandatory
    to be PSCI compliant.

update armv7 psci functions:
- psci_save_target_pc(): keep for backward compatibility with
  current platform (only save PC and force context id to 0)
  => should be removed when all platform migrate to the new API

- psci_save(): new API to use by ARMv7 platform with PSCI,
  save pc (= entry_point_address) and context_id

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-05-07 11:45:15 -04:00
Tom Rini
4549e789c1 SPDX: Convert all of our multiple license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have multiple licenses (in
these cases, dual license) declared in the SPDX-License-Identifier tag.
In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A
or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B"
as per the Linux Kernel style document.  Note that parenthesis are
allowed so when they were used before we continue to use them.

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 10:24:31 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Jagan Teki
f3df7758b5 board: sunxi: sun8i-v40: Add Bananapi M2 Berry support
Banana Pi BPI-M2 Berry is a quad-core mini single board computer
built with Allwinner V40 SoC. It features
- Quad Core ARM Cortex A7 CPU V40
- 1GB of RAM .
- microSD/SATA port..
- onboard WiFi and BT
- 4 USB A 2.0 ports
- 1 USB OTG port
- 1 HDMI port
- 1 audio jack
- DC power port

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-05-07 11:33:19 +05:30
Jagan Teki
842cc8e094 ARM: dts: sun8i: Sync r40 dtsi from Linux
Sync sun8i-r40.dtsi changes from Linux with

Merge: a406778618d0 088345fc3553
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date:   Tue Apr 24 14:15:02 2018 +1000

    Merge branch 'akpm/master'

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-07 11:31:43 +05:30
Lokesh Vutla
7ce85318cf arm: mach-omap2: cache: Explicitly enable I cache
omap-common cache enabling sequence relies on cpu_init_cp15()
(inside start.S) for enabling I-caches. But cpu_init_cp15()
can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So
enable I-caches if not enabled already.

Debugged-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-06 13:35:40 -04:00
Marek Vasut
699e831e15 ARM: rmobile: Contain CONFIG_ARCH_RMOBILE_BOARD_STRING
Pull the symbol from the boards and zap struct rmobile_sysinfo as they
are rather useless. The entire purpose of that whole machinery was to
print board name in the CONFIG_ARCH_RMOBILE_BOARD_STRING. Do that in a
far simpler and more contained manner.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-02 11:51:56 +02:00
Marek Vasut
83a64bebe4 ARM: rmobile: Convert CONFIG_ARCH_RMOBILE_BOARD_STRING to Kconfig
Convert the symbol to Kconfig, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-02 11:51:53 +02:00
Chen-Yu Tsai
9b9ceba03d sunxi: Sort dts Makefile entries for H3
The dts Makefile entries for the H3 are not ordered correctly.
Move the Nano Pi entries before the Orange Pi so they are.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-01 10:15:59 +05:30
Chen-Yu Tsai
e9392b373a sunxi: Add Libre Computer Board ALL-H3-CC H5 ver.
This patch adds a device tree file for the H5 version of the Libre
Computer Board ALL-H3-CC. It is the same board first introduced in
commit afe2754412 ("sunxi: Add support for Libre Computer Board
ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H5 SoC, and
has 4Gb DDR3 chips instead of 2Gb ones.

The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-01 10:15:58 +05:30
Chen-Yu Tsai
ad34951708 sunxi: Add Libre Computer Board ALL-H3-CC H2+ ver.
This patch adds a device tree file for the H2+ version of the Libre
Computer Board ALL-H3-CC. It is the same board first introduced in
commit afe2754412 ("sunxi: Add support for Libre Computer Board
ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H2+ SoC, and
has only two 2Gb DDR3 chips instead of four.

The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-01 10:15:58 +05:30
Chen-Yu Tsai
d7b17f1c24 sunxi: Split out common board design for ALL-H3-CC device tree
The Libre Computer Project ALL-H3-CC has three models, all using the
same board design, but with different pin compatible SoCs and amount of
DRAM.

Currently only the H3 1GB DRAM variant is supported. To support the two
other variants, first split the original device tree into a common board
design part and an SoC specific part.

The SoC part only defines which SoC is used and model name, and includes
the SoC specific dtsi file and the common design dtsi file.

Also fix up the SPDX identifier line to use the correct comment style,
and place it on the first line.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-01 10:15:58 +05:30
Tom Rini
b25f8e2112 Merge git://git.denx.de/u-boot-imx 2018-04-30 07:14:05 -04:00
Alex Kiernan
117a0e02be spl: ti: Avoid preloader_console_init if !CONFIG_SPL_SERIAL_SUPPORT
If CONFIG_SPL_SERIAL_SUPPORT is disabled then the build fails because
serial_init is undefined. Guard preloader_console_init() appropriately
to fix this.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:22 -04:00
Andre Przywara
7842b6a91e arm: move SYS_ARCH_TIMER to KConfig
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
timer) in U-Boot.
At the moment it is mandatory for ARMv8 and used by a few ARMv7 boards.
Add a proper Kconfig symbol to express this dependency properly,
allowing certain board configuration to later disable arch timer in case
there are any problems with it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[tuomas: rebase + fix conflicts and resync with moveconfig & use select]
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2018-04-28 18:30:43 -04:00
Masahiro Yamada
7325f6cfdc distro: use imply to enable DISTRO_DEFAULTS as SoC default
The default of DISTRO_DEFAULTS is messy.  Using the 'imply' keyword
is equivalent and cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-28 10:42:35 -04:00
Heinrich Schuchardt
b60cfb6a01 powerpc: fix typo in kgdb.c
%s/alingment/alignment/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-04-28 10:42:35 -04:00
Tom Rini
3b6407b8ed clang: Update documentation
As of clang-5.0, things have changed a bit.  First, we cannot
automatically guess -target values as if we do not pass one with CC then
cc-option will fail.  Second, to disable movt/movw relocations the
argument has become -mno-movt.

Related to the target part, we cannot use arm-none-eabi as that ends up
being too generic of an ARM target for things like say rpi_3_32b to
work.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:49 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Adam Ford
f1b1f77060 Convert CONFIG_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_SPI

This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver.  For now, just update
the CONFIG tests.  This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:11 -04:00
Mans Rullgard
07a8f79ee8 ARM: mxs: support full SPL framework
This allows using the full SPL framework on mxs devices.  In this
mode, the u-boot.sb image loaded by the boot ROM contains only the
SPL which then loads U-Boot proper or a kernel in falcon mode.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
33ea119382 ARM: mxs: move spl data
With full SPL enabled, the loaded image overwrites the mxs_spl_data
location.  Moving it a slightly lower address fixes this.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
68f835557c ARM: spl: include arm/thumb glue sections
When building in Thumb mode, the linker might generate mode switching
stubs in .glue sections.  Include these in the final link.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
da372af6e4 ARM: arm926ejs: fix lowlevel_init call
The code attempts to preserve the value of LR by storing it in R12/IP
across the lowevel_init() call.  However, this register is not saved
by the callee.  Use a register that guaranteed to be preserved instead.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
9482aeda66 ARM: mxs: make lowlevel_init() weak
With the full SPL framework enabled, lowlevel_init() is required.
Make the empty stub weak so boards can override it.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Tom Rini
641bce2635 Merge git://git.denx.de/u-boot-sh 2018-04-26 22:08:58 -04:00
Marek Vasut
bb6d2ff2ac ARM: rmobile: Update E2 Alt
The E2 Alt port was broken since some time. This patch updates
the E2 Alt port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Marek Vasut
49aefe300a ARM: rmobile: Update M2-N Gose
The M2-N Gose port was broken since some time. This patch updates
the M2-N Gose port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Marek Vasut
e6027e6f45 ARM: rmobile: Update H2 Lager
The H2 Lager port was broken since some time. This patch updates
the H2 Lager port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Sébastien Szymanski
ea77217828 imx6ul: opos6ul: in Serial Downloader boot mode use ymodem
When booting in Serial Downloader mode load the U-Boot image using
ymodem.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26 09:34:16 +02:00
Sébastien Szymanski
30754ef77c imx6ul: opos6ul: add SPL_DM support
Since commit commit 152038ea18 ("i.MX6UL: icore: Add SPL_OF_CONTROL
support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support
makes the board boot again.

Fixes: commit 152038ea18 ("i.MX6UL: icore: Add SPL_OF_CONTROL support")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26 09:34:00 +02:00
Mark Jonas
5ebf9ad96c arm,imx6: fix PAD_CTL_SPEED_LOW constant
For most i.MX6 processors the PAD_CTL_SPEED_LOW constant is the same.
Only the i.MX6 SoloLite is an exemption. So far the code did not
consider that. Additionally, for a few i.MX6 processors the code used
the wrong value for the constant.

This patch fixes the PAD_CTL_SPEED_LOW constant for:
 - i.MX6 Solo [1]
 - i.MX6 DualLite [1]
 - i.MX6 Dual [2]
 - i.MX6 Quad [2]
 - i.MX6 DualPlus [3]
 - i.MX6 QuadPlus [3]

Before, it was already correct for:
 - i.MX6 SoloLite [4]
 - i.MX6 SoloX [5]
 - i.MX6 UtraLite [6]
 - i.MX6 ULL [7]

[1] https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf
[2] https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf
[3] https://www.nxp.com/docs/en/reference-manual/iMX6DQPRM.pdf
[4] https://www.nxp.com/docs/en/reference-manual/IMX6SLRM.pdf
[5] https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf
[6] https://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf
[7] https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf

Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-04-26 08:55:42 +02:00
Kever Yang
c3c0331db1 rockchip: enable SYS_NS16550 for all SoCs by default
All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Version-changes: 2
- use imply instead of select

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
cb7116afe8 rockchip: rk322x: update MACRO for back-to-brom
The MACRO has been update after:
ee14d29 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
We need to update the C code for it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Patrick Uiterwijk
ced3c10fd2 arm: rockchip: make_fit_atf: remove unneeded imports
These imports are entirely unused in the entire script.

Signed-off-by: Patrick Uiterwijk <patrick@puiterwijk.org>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00