Commit graph

15 commits

Author SHA1 Message Date
Bin Meng
3ff11aaa50 x86: baytrail: acpi: Hide internal UART per GNVS setting
If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
79c2c257cf x86: acpi: Pack global NVS into ACPI table
Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
2047390abc x86: baytrail: Introduce ACPI global NVS
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
3498cc9775 x86: acpi: Make irqroute.asl common
The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
0d71511a2a x86: acpi: Create a common irqlinks ASL file
Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
7bfe0da4d2 x86: baytrail: Add GPIO ASL description
Since BayTrail, Intel starts to use new GPIO IPs in their chipset.
This adds the GPIO ASL, so that OS can load corresponding drivers
for it. On Linux, this is BayTrail pinctrl driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
fa427438bd x86: baytrail: Add internal UART ASL description
BayTrail integrates an internal ns15550 compatible UART (PNP0501).
Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer
revision one IRQ4 is being used for ISA compatibility. Handle this
correctly in the ASL file.

Linux does not need this ASL, but Windows need this to correctly
discover a COM port existing in the system so that Windows can
show it in the 'Device Manager' window, and expose this COM port
to any terminal emulation application.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
42f8ebfd23 x86: baytrail: Add platform ASL files
This adds basic BayTrail platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for
now. They will be added in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
2b7ff26115 x86: Drop asm/arch/gpio.h
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
4ce022d396 x86: fsp: Move struct fspinit_rtbuf definition to chipset header
All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf
as defined by the 1.0 spec, however there are FSPs that does not
follow 1.0 spec (possible due to that FSP predates the 1.0 spec),
and future FSP binary that is complaint to v1.1 spec defines an
optional paltform-specific runtime data in the struct fspinit_rtbuf.
Hence move the definition to chipset header.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
cb379a34c4 x86: fsp: Rename shared_data to fsp_config_data
FSP has several config data like UPD, HDA verb table which can be
overridden or provided by bootloader. Currently in U-Boot only UPD
is handled via struct shared_data. To accommodate any platform, we
rename shared_data to fsp_config_data and move the definition from
common place fsp_support.h to platform-specific place fsp_configs.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:14 +08:00
Bin Meng
da60fb7934 x86: fsp: Do not assert VPD_IMAGE_REV when DEBUG
When using different release version of Intel FSP, the VPD_IMAGE_REV
is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304).
Remove the asserting of this so that U-Boot does not hang in a debug
build.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Bin Meng
3e79a4ab26 x86: baytrail: Update UPD setting for FSP Gold4 release
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Gabriel Huau
4a34e4b86f x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:49 -06:00
Simon Glass
3a1a18ff18 x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06 12:07:39 -07:00