Commit graph

1559 commits

Author SHA1 Message Date
Stefan Roese
9e5c2a755a mtd: nand: spi: Add Gigadevice SPI NAND support
This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-04 18:24:24 +05:30
Stefan Roese
881e4fc206 sf: Add XMC xm25qh64a and xm25qh128a entries
This patch adds support for 2 new XMC (Wuhan Xinxin Semiconductor
Manufacturing Corp) SPI NOR chips.

This support can be enabled by selecting the SPI_FLASH_XMC Kconfig
option.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-04 18:21:23 +05:30
Miquel Raynal
5db66b3aee cmd: mtd: add 'mtd' command
There should not be a 'nand' command, a 'sf' command and certainly not
a new 'spi-nand' command. Write a 'mtd' command instead to manage all
MTD devices/partitions at once. This should be the preferred way to
access any MTD device.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-02 22:12:32 +05:30
Miquel Raynal
2a74930da5 mtd: mtdpart: implement proper partition handling
Instead of collecting partitions in a flat list, create a hierarchy
within the mtd_info structure: use a partitions list to keep track of
the partitions of an MTD device (which might be itself a partition of
another MTD device), a pointer to the parent device (NULL when the MTD
device is the root one, not a partition).

By also saving directly in mtd_info the offset of the partition, we
can get rid of the mtd_part structure.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-02 22:12:32 +05:30
Miquel Raynal
ff4afa8a98 mtd: uboot: search for an equivalent MTD name with the mtdids
Using an MTD device (resp. partition) name in mtdparts is simple and
straightforward. However, for a long time already, another name was
given in mtdparts to indicate a device (resp. partition) so the
"mtdids" environment variable was created to do the match.

Let's create a function that, from an MTD device (resp. partition)
name, search for the equivalent name in the "mtdparts" environment
variable thanks to the "mtdids" string.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-02 22:12:32 +05:30
Miquel Raynal
21cc1fb5af mtd: mtdpart: add a generic mtdparts-like parser
The current parser is very specific to U-Boot mtdparts implementation.
It does not use MTD structures like mtd_info and mtd_partition. Copy
and adapt the current parser in drivers/mtd/mtd-uclass.c (to not break
the current use of mtdparts.c itself) and write some kind of a wrapper
around the current implementation to allow other commands to benefit
from this parsing in a user-friendly way.

This new function will allocate an mtd_partition array for each
successful call. This array must be freed after use by the caller.
The given 'mtdparts' buffer pointer will be moved forward to the next
MTD device (if any, it will point towards a '\0' character otherwise).

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-02 22:12:31 +05:30
Miquel Raynal
e9f62db64b mtd: uclass: add probe function
The user might want to trigger the probe of any MTD device, export these
functions so they can be called from a command source file.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-10-02 22:12:31 +05:30
Miquel Raynal
b0036f7004 mtd: mtdpart: balance debug messages
Balance debug message in the partition allocation/removal process in
order to keep track of them more easily.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
4048a5c519 mtd: declare MTD_PARTITIONS symbol in Kconfig
UBI selects MTD_PARTITIONS which is the symbol to compile
drivers/mtd/mtdpart.c. Unfortunately, the symbol was not defined in
Kconfig and this worked only with board files defining it. Fix this by
adding a boolean in Kconfig so boards defined by defconfig files only
will work as expected.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
515d021261 mtd: spinand: Add initial support for the MX35LF2GE4AB chip
Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Boris Brezillon
6f041ccabb mtd: spinand: Add initial support for the MX35LF1GE4AB chip
Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Frieder Schrempf
3181c0a622 mtd: spinand: Add initial support for Winbond W25M02GV
Add support for the W25M02GV chip.

Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Peter Pan
883d8778ae mtd: spinand: Add initial support for Micron MT29F2G01ABAGD
Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Peter Pan
0a6d6bae03 mtd: nand: Add core infrastructure to support SPI NANDs
Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework supports the following features:

- single/dual/quad IO modes
- on-die ECC

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Boris Brezillon
b95db8d33a mtd: nand: Add core infrastructure to deal with NAND devices
Add an intermediate layer to abstract NAND device interface so that
some logic can be shared between SPI NANDs, parallel/raw NANDs,
OneNANDs, ...

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
3657b2f4a3 mtd: rename nand into rawnand in Kconfig prompt
Sync the Kconfig raw NAND entry title with the code architecture.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
a430fa06a4 mtd: move NAND files into a raw/ subdirectory
NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
ce9bdc8743 mtd: move all flash categories inside MTD submenu
There is no reason to have NAND, SPI flashes and UBI sections outside of
the MTD submenu in Kconfig.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
d02f1d36ec mtd: move definitions to enlarge their range
Some helpers might be useful in a future 'mtd' U-Boot command to parse
MTD device list.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Miquel Raynal
ca040d8512 mtd: Fallback to ->_read/write() when ->_read/write_oob() is missing
Some MTD sublayers/drivers are implementing ->_read/write() and
not ->_read/write_oob().

While for NAND devices both are usually valid, for NOR devices, using
the _oob variant has no real meaning. But, as the MTD layer is supposed
to hide as much as possible the flash complexity to the user, there is
no reason to error out while it is just a matter of rewritting things
internally.

Add a fallback on mtd->_read() (resp. mtd->_write()) when the user calls
mtd_read_oob() (resp. mtd_write_oob()) while mtd->_read_oob() (resp.
mtd->_write_oob) is not implemented. There is already a fallback on the
_oob variant if the former is used.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2018-09-20 20:10:49 +05:30
Boris Brezillon
8fad769f1e mtd: Add sanity checks in mtd_write/read_oob()
Unlike what's done in mtd_read/write(), there are no checks to make sure
the parameters passed to mtd_read/write_oob() are consistent, which
forces implementers of ->_read/write_oob() to do it, which in turn leads
to code duplication and possibly errors in the logic.

Do general sanity checks, like ops fields consistency and range checking.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Peter Pan <peterpandong@micron.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
[Miquel: squashed the fix about the chip's size check]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Ezequiel Garcia
5f50d82d89 mtd: Uninline mtd_write_oob and move it to mtdcore.c
There's no reason for having mtd_write_oob inlined in mtd.h header.
Move it to mtdcore.c where it belongs.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Boris Brezillon
596cf083da mtd: Fallback to ->_read/write_oob() when ->_read/write() is missing
Some MTD sublayers/drivers are implementing ->_read/write_oob() and
provide dummy wrappers for their ->_read/write() implementations.
Let the core handle this case instead of duplicating the logic.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
David Sniatkiwicz
e76afd8409 fix: nand: pxa3xx: Add WA for eliminating flash ready timeout
add delay before processing the status flags in pxa3xx_nand_irq().

Signed-off-by: David Sniatkiwicz <davidsn@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
c: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Konstantin Porotchkin
b7b3f2c8bb nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NAND
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI).

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Konstantin Porotchkin
e9a0777f85 nand: pxa3xx: cosmetic: add comments to the timing layout structures
Add comments with timing parameter names and some details about
nand layout fileds.
Remove unneeded definition.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Konstantin Porotchkin
2057eb0b16 fix: nand: Replace hardcoded page chunk size with calculated one
Replace the hardcoded value of page chink with value that
depends on flash page size and ECC strength.
This fixes nand access errors for 2K page flashes with 8-bit ECC.
Move the initial flash commannd function assignment past the ECC
structures initialization for eliminating usage of hardcoded page
chunk size value.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Konstantin Porotchkin
b0d7c106c9 mtd: nand: pxa3xx: add support for Toshiba flash
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Victor Axelrod
ac56a3b30c mtd: nand: pxa3xx: add support for 2KB 8-bit flash
Add support for 2KB page 8-bit ECC strength flash layout

Signed-off-by: Victor Axelrod <victora@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Boris Brezillon
f3d235702d mtd: nand: pxa3xx: Fix READOOB implementation
In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
driver must read the whole spare area (64 bytes in case of a 2k page,
16 bytes for a 512 page). The driver was only reading the free OOB
bytes, which was leaving some unread data in the FIFO and was somehow
leading to a timeout.

We could patch the driver to read ->spare_size + ->ecc_size instead of
just ->spare_size when READOOB is requested, but we'd better make
in-band and OOB accesses consistent.
Since the driver is always accessing in-band data in non-raw mode (with
the ECC engine enabled), we should also access OOB data in this mode.
That's particularly useful when using the BCH engine because in this
mode the free OOB bytes are also ECC protected.

Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
Cc: stable@vger.kernel.org
Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:02:34 +02:00
Ofer Heifetz
b47f677931 mtd: nand: pxa3xx_nand: add support for partial chunks
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.

When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.

When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:

| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |

So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.

When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:

| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC |

So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.

Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.

To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.

In order to implement reading of the last chunk, this commit:

 - Adds a number of new fields to the pxa3xx_nand_info to describe how
   many full chunks and how many chunks we have, the size of full
   chunks and partial chunks, both in terms of data area and spare
   area.

 - Fills in the step_chunk_size and step_spare_size variables to
   describe how much data and spare should be read/written for the
   current read/program step.

 - Reworks the state machine to accommodate doing the additional read
   or program step when a last partial chunk is used.

This commit is taken from Linux:
'commit c2cdace755b'
("mtd: nand: pxa3xx_nand: add support for partial chunks")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
7efd95eacf mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.

This commit is taken from Linux:
'commit 154f50fbde53'
("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
b87ae6f587 mtd: pxa3xx_nand: Fix initial controller configuration
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.

Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.

Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.

This commit is taken from Linux:
'commit 66e8e47eae65'
("mtd: pxa3xx_nand: Fix initial controller configuration")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
6bbe7f681f mtd: pxa3xx_nand: Increase the initial chunk size
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.

However, the initial chunk size is used in a non-split way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).

Thus, the initial chunk size should be 2048 as well.

On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:

  [..]
  pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
  pxa3xx-nand f10d0000.nand: Wait time out!!!
  nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
  nand: Micron MT29F8G08ABABAWP
  nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224

This commit is taken from Linux:
'commit c7f00c29aa8'
("mtd: pxa3xx_nand: Increase the initial chunk size")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
94488612cb nand: pxa3xx: Increase READ_ID buffer and make the size static
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.

This commit is taken from Linux:
'commit b226eca2088'
("nand: pxa3xx: Increase READ_ID buffer and make the size static")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
cd11b2b457 mtd: nand: pxa3xx-nand: fix random command timeouts
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase

This patch is taken from Linux:
'commit 21fc0ef9652f'
("mtd: nand: pxa3xx-nand: fix random command timeouts")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
658999244a mtd: nand: pxa3xx_nand: fix early spurious interrupt
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.

This commit is taken from Linux:
'commit 0b14392db2e'
("mtd: nand: pxa3xx_nand: fix early spurious interrupt")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
d3859d1b53 mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()
Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
8cdcf672c5 mtd: nand: pxa3xx_nand: use nand_to_mtd()
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Ofer Heifetz
144532242e mtd: nand: pxa3xx_nand: Increase initial buffer size
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).

ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.

This commit is taken from Linux:
'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Masahiro Yamada
e8f65763ef mtd: nand: denali: fix unaligned cache operations on ARMv7 SoCs
If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".

=> nand info

Device 0: nand0, sector size 256 KiB
  Page size       4096 b
  OOB size         224 b
  Erase size    262144 b
  subpagesize     4096 b
  options     0x00104200
  bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
  ...

The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]
2018-09-10 14:08:22 -04:00
Tom Rini
b8a1f47be3 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-08-13 12:34:55 -04:00
Darwin Dingel
1711add3dc mtd: nand: fsl_ifc: Fix handling of bitflips in erased pages
This is a fix made for the fsl_ifc_nand driver on linux kernel by
Pavel Machek and is applied to uboot. It is currently on applied on
linux-mtd.

https://patchwork.kernel.org/patch/9758117/

IFC always raises ECC errors on erased pages. It is only ignored when
the buffer is checked for all 0xFF by is_blank(). The problem is a
single bitflip will cause is_blank() and then mtd_read to fail. The fix
makes use of nand_check_erased_ecc_chunk() to check for empty pages
instead of is_blank(). This also makes sure that reads are made at ECC
page size granularity to get a proper bitflip count. If the number of
bitflips does not exceed the ECC strength, the page is considered empty
and the bitflips will be corrected when data is sent to the higher
layers (e.g. ubi).

Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz>
Cc: Pavel Machek <pavel@denx.de>
Cc: Scott Wood <oss@buserror.net>
Acked-by: Pavel Machek <pavel@denx.de>
[Kurt: Replaced dev_err by printf due to compiler warnings]
Tested-by: Kurt Kanzenbach <kurt@linutronix.de>
Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:51 -07:00
Michal Simek
13f451bf56 spi: Kconfig: Create ISSI Kconfig entry
Add ISSI to Kconfig to make it selectable via menuconfig.
Also convert all current platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Tom Rini
bb694d4e89 Merge branch 'master' of git://git.denx.de/u-boot-spi 2018-08-04 19:41:43 -04:00
Clément Laigle
04d57b1d58 mtd: add spi flash id s25fl128l
Add support for SPANSION s25fl128l

Signed-off-by: Clément Laigle <c.laigle@catie.fr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed , at the end of } ]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-03 11:09:53 +05:30
Mylène Josserand
850bdafa50 mtd: nand: sunxi: Return on set_feature only when not ENOTSUPP
Return the error code of the set_features function only if
the error code is not ENOTSUPP. Otherwise, if this function
is not supported, it will return and fail to initialize the
NAND.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-31 20:45:50 +05:30
Mylène Josserand
cbe9ea26e3 mtd: nand: nand_base: Convert EINVAL into ENOTSUPP
Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES
is not supported.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-31 20:45:42 +05:30
Masahiro Yamada
4a610fada1 mtd: nand: denali: correct buffer alignment for DMA transfer
The NAND framework makes sure to pass in the buffer with at least
chip->buf_align alignment.  Currently, the Denali NAND driver only
requests 16 byte alignment.  This causes unaligned cache operations
for the DMA transfer.

[Error Example]

=> nand read 81000010 0 1000

NAND read: device 0 offset 0x0, size 0x1000
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
 4096 bytes read: OK

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:52 +09:00
Tom Rini
f0306a145b Merge branch 'master' of git://git.denx.de/u-boot-imx
trini: Update colibri-imx6ull to use Kconfig for mtdparts related
options.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-23 13:37:42 -04:00