Commit graph

72664 commits

Author SHA1 Message Date
Ying-Chun Liu (PaulLiu)
a606106402 doc: device-tree-bindings: regulator: anatop regulator
Document the bindings for fsl,anatop-regulator

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-20 07:31:12 -04:00
Ying-Chun Liu (PaulLiu)
6ab0286ae1 power: regulator: add driver for ANATOP regulator
Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-20 07:31:12 -04:00
Heinrich Schuchardt
ec611871f3 cmd: CONFIG_CMD_MMC depends on CONFIG_MMC
Trying to compile with CONFIG_CMD_MMC=y and CONFIG_MMC=n leads to errors:

riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmcops':
cmd/mmc.c:984: undefined reference to `get_mmc_num'
riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmc_setdsr':
cmd/mmc.c:873: undefined reference to `find_mmc_device'

Add missing dependency.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-20 07:31:12 -04:00
Tim Harvey
935e0b0ecd net: octeontx: smi: fix mii probe
The fdt node offset is apparently not set properly when probed
causing no MDIO busses to be found. Fix this by obtaining the
offset.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20 07:31:12 -04:00
Suneel Garapati
98a8180dca drivers: ata: ahci: update max id if it is more than available ports
After check for maximum between max id and available ports, also check
if available port count is less than max id and update.

In the case of the CN8030 OcteonTX SoC max_id needs to be reduced to
the number of ports found otherwise the following occurs on a scan:

GW6404-B> scsi scan
scanning bus for devices...
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq ilck stag pm led clo only pmp fbss pio slum part ccc
apst
  Device 0: (0:0) Vendor: ATA Prod.: SanDisk SD8SFAT0 Rev: Z233
            Type: Hard Disk
            Capacity: 61057.3 MB = 59.6 GB (125045424 x 512)
"Synchronous Abort" handler, esr 0x96000006
elr: 000000000052f824 lr : 000000000052fa10 (reloc)
elr: 000000007fee9824 lr : 000000007fee9a10
x0 : 0000000000000001 x1 : 0000000000000001
x2 : 000000007bea3528 x3 : 000000007bea3580
x4 : 0000000000000200 x5 : 0000000000000000
x6 : 0000000000000002 x7 : 000000007bea3540
x8 : 00000000fffffff8 x9 : 0000000000000008
x10: 00000000000186a0 x11: 000000000000000d
x12: 0000000000000006 x13: 000000000001869f
x14: 0000000000000007 x15: 00000000ffffffff
x16: 000000007ff439a5 x17: 000000007ff5730c
x18: 000000007bea9de0 x19: 000000007ff7a580
x20: 000000007bec79f8 x21: 0000000000000000
x22: 000000007bea3580 x23: 0000000000000000
x24: 0000000000000000 x25: 000000007bec7a00
x26: 00000000ffffffc0 x27: 000000007bec79d0
x28: 000000007beb51c0 x29: 000000007bea3480

Code: 91246800 940130c2 12800000 1400004f (b9402ae0)
Resetting CPU ...

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20 07:31:12 -04:00
Tim Harvey
8c64347b7e drivers: net: octeontx: fix QSGMII
Revert a change that occured between the Marvell SDK-10.1.1.0
and SDK-10.3.1.1 which broke QSMII phy support.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-20 07:31:12 -04:00
Tim Harvey
9889a8e562 arm: octeontx: enable WDT_SBSA
The OcteonTX uses ARM's SBSA Watchdog device

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20 07:31:12 -04:00
Tim Harvey
8bb5a66e5b arm: octeontx: support generic distro config
Support Generic Distro Default config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20 07:31:12 -04:00
Tim Harvey
ab7f8d1850 arm: octeontx: move CONFIG_SUPPORT_RAW_INITRD to configs
Move CONFIG_SUPPORT_RAW_INITRD out of the octeontx_common header
and into the defconfig files.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-20 07:31:12 -04:00
Karl Beldan
227c53de87 lz4: Fix unaligned accesses
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
2021-04-20 07:31:12 -04:00
Reinoud Zandijk
0a527fda78 Fix IDE commands issued, fix endian issues, fix non MMIO
Fixes IDE issues found on the Malta board under Qemu:

1) DMA implied commands were sent to the controller in stead of the PIO
variants. The rest of the code is DMA free and written for PIO operation.

2) direct pointer access was used to read and write the registers instead
of the inb/inw/outb/outw functions/macros. Registers don't have to be
memory mapped and ATA_CURR_BASE() does not have to return an offset from
address zero.

3) Endian isues in ide_ident() and reading/writing data in general. Names
were corrupted and sizes misreported.

Tested malta_defconfig and maltael_defconfig to work again in Qemu.

Signed-off-by: Reinoud Zandijk <reinoud@NetBSD.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-04-20 07:31:12 -04:00
Wasim Khan
57c675d699 sandbox: enable IRQ using select for sandbox architecture
Enable IRQ using select for sandbox architecture.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-20 07:31:35 -04:00
Wasim Khan
543d091edb arch: Kconfig: enable IRQ using select for x86 architecture
use 'select' to enable IRQ as it does not have architecture
specific dependency.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-20 07:31:31 -04:00
Wasim Khan
504f8648f0 arch: arm: update Kconfig to select IRQ when GIC_V3_ITS is enabled
GIC_V3_ITS uses UCLASS_IRQ driver. Update Kconfig to select
IRQ when GIC_V3_ITS is enabled.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
2021-04-20 07:31:12 -04:00
Wasim Khan
182c5f1efb misc: make CONFIG_IRQ selectable for all platforms
UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ
selectable for all platforms.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-20 07:31:12 -04:00
Hou Zhiqiang
6f6876a0c0 arm64: gic-v3-its: Clear the Pending table before enabling LPIs
The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables
must contain only zeros on initial allocation, and this must be visible
to the Redistributors, or else the effect is UNPREDICTABLE".

And as the following statement, we here clear the whole Pending tables
instead of the first 1KB.
"An LPI Pending table that contains only zeros, including in the first 1KB,
indicates that there are no pending LPIs.
The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However,
if the first 1KB of the LPI Pending table and the rest of the table contain
only zeros, this must indicate that there are no pending LPIs."

And there isn't any pending LPI under U-Boot, so it's unnecessary to
load the contents of the Pending table during the enablement, then set
the GICR_PENDBASER.PTZ flag.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-20 07:31:12 -04:00
Neil Armstrong
612729b178 boards: amlogic: update documentation for PCIe support
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Neil Armstrong
2dbe777753 configs: meson64: add NVME boot target
Let's add a boot target for NVMe so we can do a full boot over NVMe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Neil Armstrong
8f4f65ed6a configs: khadas-vim3: enable PCIe and NVMe
Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs
connected on the M.2 slot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Neil Armstrong
c8dd2ad696 arm: dts: meson-khadas-vim3: enable PCIe in U-boot
Enable PCIe by default in u-boot, this should eventually be made dynamic
in the runtime board config depending on the MCU configuration.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Neil Armstrong
628adbd70e phy: meson-g12a-usb3-pcie: add support for PCIe ops
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Neil Armstrong
2696a41ef1 clk: meson-g12a: add PCIe gates
Add missing gates used for PCIe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Stefan Agner
30d083d226 arm64: dts: meson: odroidc2: readd PHY reset properties
The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.

Fixes: dd5f2351e9 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-20 07:30:04 -04:00
Tom Rini
eed05148c2 - fix Ethernet on Odroid-C2 by re-adding old bindings style PHY reset
- add G12A PCIe clock gates
 - add G12A PCIe PHY OPs
 - enable PCIe for Khadas VIM3/VIM3L boards DT
 - enable PCIe and NVME for Khadas VIM3/VIM3L boards config
 - update Amlogic board documentation for PCIe support
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Merge tag 'u-boot-amlogic-20210419' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- fix Ethernet on Odroid-C2 by re-adding old bindings style PHY reset
- add G12A PCIe clock gates
- add G12A PCIe PHY OPs
- enable PCIe for Khadas VIM3/VIM3L boards DT
- enable PCIe and NVME for Khadas VIM3/VIM3L boards config
- update Amlogic board documentation for PCIe support
2021-04-19 13:35:23 -04:00
Tom Rini
5fa1e2ffeb Second set of u-boot-atmel features for 2021.07 cycle
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Merge tag 'u-boot-atmel-2021.07-b' of https://source.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features for 2021.07 cycle:

This small feature set include support for 5th PIO bank on pio4 pinctrl
driver and a fix for the SPL on sama5d3.
2021-04-19 11:34:17 -04:00
Alexandru Gagniuc
58b504e5e1 Revert "spl: Drop bd_info in the data section"
This reverts commit 38d6b7ebda.

struct global_data contains a pointer to the bd_info structure. This
pointer was populated spl_set_bd() to a pre-allocated bd_info in the
".data" section. The referenced commit replaced this mechanism to one
that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y.
which very few boards do.

The result is that (struct global_data)->bd is NULL in SPL on most
platforms. This breaks falcon mode, since arch_fixup_fdt() tries to
access (struct global_data)->bd and set the "/memory" node in the
devicetree. The result is that the "/memory" node contains garbage
values, causing linux to panic() as it sets up the page table.

Instead of trying to fix the mess, potentially causing other issues,
revert to the code that worked, while this change is reworked.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-04-19 11:34:01 -04:00
Neil Armstrong
fcf3c9deae boards: amlogic: update documentation for PCIe support
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Neil Armstrong
83752094d1 configs: meson64: add NVME boot target
Let's add a boot target for NVMe so we can do a full boot over NVMe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Neil Armstrong
ea001950af configs: khadas-vim3: enable PCIe and NVMe
Now we have PCIe, let's also enable NVMe to access an eventual NVMe SSDs
connected on the M.2 slot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Neil Armstrong
4a892b5554 arm: dts: meson-khadas-vim3: enable PCIe in U-boot
Enable PCIe by default in u-boot, this should eventually be made dynamic
in the runtime board config depending on the MCU configuration.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Neil Armstrong
320160cd97 phy: meson-g12a-usb3-pcie: add support for PCIe ops
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Neil Armstrong
3034a1eda3 clk: meson-g12a: add PCIe gates
Add missing gates used for PCIe.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Stefan Agner
a246e21351 arm64: dts: meson: odroidc2: readd PHY reset properties
The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2. The PHY seems to need proper reset timing to be functional
in U-Boot and Linux afterwards. Readd the old PHY reset bindings for
dwmac until we support the new bindings in the PHY node.

Fixes: dd5f2351e9 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Manuel Reis
b0080ae1bb ARM: dts: at91: sama5d3: add u-boot properties to sama5d3 pit timer
in the early SPL boot stage whenever there is a call to udelay,
dm_timer_init fails to find the pit timer whenever it traverses
the device tree, if this property is not present

Signed-off-by: Manuel Reis <mluis.reis@gmail.com>
CC: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-04-19 10:38:52 +03:00
Eugen Hristev
53d7664711 ARM: dts: at91: sama7g5: change pinctrl compatible to sama7g5
Change the pinctrl compatible to sama7g5, the right one for this product.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-04-19 10:38:49 +03:00
Eugen Hristev
e1038ac0cb gpio: atmel_pio4: add support for sama7g5 pio4 version with 5 banks
Add support for sama7g5 pinctrl variant, with 5 banks with a degraded
8 line only 5th bank.
Based on Linux Kernel implementation.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-04-19 10:38:49 +03:00
Tom Rini
3a9aaefcaa Pull request for efi-2021-07-rc1-2
Documentation:
 	man-page for fatinfo
 
 Bug fixes:
 	memory leak in efi_capsule_scan_dir()
 	incorrect invocations of EFI_CALL macro creating ESRT table
 	buffer overflow in tcg2_create_digest()
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Merge tag 'efi-2021-07-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-07-rc1-2

Documentation:
	man-page for fatinfo

Bug fixes:
	memory leak in efi_capsule_scan_dir()
	incorrect invocations of EFI_CALL macro creating ESRT table
	buffer overflow in tcg2_create_digest()
2021-04-18 08:47:27 -04:00
Tom Rini
c6ae5e9869 Merge https://source.denx.de/u-boot/custodians/u-boot-usb
This is a patchset which makes away with the .bind() controller indexing
workaround which was broken since before v2021.04, and then adds PHY
support and MX8M support on top of that. Better add it into the release
early to get as much testing as possible done, because this really does
a lot of changes to the ehci-mx6 driver.
2021-04-18 08:46:58 -04:00
Tom Rini
2fbc804715 Merge tag 'ti-v2021.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Support for pinmux status command on beaglebone
- Updates for MMC speed modes for J721e-evm
- Fix MMC booting on omap35_logic_somlv board
2021-04-18 08:46:39 -04:00
Tom Rini
6e052b854a Merge branch '2021-04-16-env-updates'
- SPI Flash ENV improvements / cleanups
- Redundant support for FAT
- Assorted bugfixes
2021-04-18 08:44:25 -04:00
Marek Vasut
d08cdc223d ARM: imx8m: verdin-imx8mm: Enable USB Host support
Enable USB host support on MX8MM Verdin.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
5e7e2a8e4f usb: ehci-mx6: Add iMX8M support
The iMX8M uses nop PHY, select PHY and NOP_PHY automatically.
Otherwise, the DM capable driver is now perfectly compatible.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
f444f8986b usb: ehci-mx6: Fix aarch64 build warnings
Fix cast from pointer to integer of different size by casting the
pointer to uintptr_t instead of uint32_t, the former has correct
size on both 32bit and 64bit architectures.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
e87015ff05 usb: ehci-mx6: Add fsl,imx7d-usb compatible string
Add new compatible string, used by some more up-to-date DTs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
1aae8a35a2 usb: ehci-mx6: Set default CONFIG_MXC_USB_PORTSC if not defined
There is now multiple copies of CONFIG_MXC_USB_PORTSC in configs set to
PORT_PTS_UTMI | PORT_PTS_PTW, which is in fact the default register value
for MX6, MX7 and MX7ULP. Define the default value of CONFIG_MXC_USB_PORTSC
in the driver and use it in case CONFIG_MXC_USB_PORTSC is not defined in
config, to reduce the duplication.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
50d0146cb7 usb: ehci-mx6: Add generic EHCI PHY support
In case PHY support is enabled, use the generic EHCI PHY support
to start and stop the PHY.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
6443a3bc40 usb: ehci-mx6: Use portnr from DT in DM case
In case the platform uses DM, determine port number, which is
used as offset in USBMISC registers, from PHY node DT aliases,
just like Linux does.

Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
668646995f usb: ehci-mx6: Pass MISC address to usb_oc_config()
Instead of passing ad-hoc sequence number to usb_oc_config(), pass in
the USB MISC address itself. The USB MISC address comes from DT in DM
case, and from the old method using controller index in non-DM case.

Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
849763b963 usb: ehci-mx6: Split usb_power_config()
Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP
addresses instead of ad-hoc sequence numbers. This is only applicable
on legacy systems which do not implement proper PHY support. Once PHY
support is available, parts of this can be removed altogether and moved
to the PHY driver, similar to Linux phy-mxs-usb.c .

Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00
Marek Vasut
eb64f598dc usb: ehci-mx6: Pass PHY address to usb_*_phy*()
Instead of passing ad-hoc index to USB PHY handling functions and then
try and figure out the PHY address, pass in the PHY address itself. For
DM case, this address comes easily from DT. For non-DM case, the previous
method is still present, however the non-DM case will soon be removed.

Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:36 +02:00