Commit graph

10 commits

Author SHA1 Message Date
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Simon Glass
8c103c33fb dm: dts: Convert driver model tags to use new schema
Now that Linux has accepted these tags, move the device tree files in
U-Boot over to use them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14 09:43:26 -07:00
Amit Kumar Mahapatra
6e38e2ea79 arm64: zynqmp: Set qspi tx-buswidth to 4
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
T Karthik Reddy
d93fbac512 arm64: zynqmp: Fix zynqmp mini qspi max frequency
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.

With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
T Karthik Reddy
7831292fc9 arm64: zynqmp: Change spi-max-frequency for qspi mini
Change mini u-boot qspi spi-max-frequency to 108Mhz, make the
frequency similar to full u-boot qspi flash spi-max-frequency.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24 13:07:58 +02:00
Michal Simek
d31f1c9236 arm64: zynqmp: Update Copyright years to 2020
Trivial change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
b96b695f2c arm64: zynqmp: Switch spi-flash to jedec, spi-nor compatible
Change has been done across the whole tree only zynqmp-mini-qspi hasn't
been fixed.
Origin changed done by commit ffd4c7c2ec
("dts: switch spi-flash to jedec, spi-nor compatible")

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:41:27 +02:00
Siva Durga Prasad Paladugu
3b4146f133 arm64: zynqmp: Define label for flash node
Define a label for flash node so that it can be
referenced easily as required.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:51:34 +02:00
Siva Durga Prasad Paladugu
8bc8991f22 arm64: zynqmp: Add spi-flash compatible string to flash node
spi-flash compatible string is needed for reading tx and rx bus
widths, hence add this compatible string to flash node.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16 11:51:34 +02:00
Siva Durga Prasad Paladugu
14ed50a4bf arm64: zynqmp: Add QSPI flash mini u-boot configuration
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint of internal memory. This
configuration has only required qspi flash support and it
uses DCC as serial.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:56 +02:00