Commit graph

17439 commits

Author SHA1 Message Date
Simon Glass
6cc915b5fb arm: powerpc: Tidy up code style for cache functions
Remove the unwanted space before the bracket.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
62270f4395 common: Move some SMP functions out of common.h
These functions belong in cpu_func.h so move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
30c7c43473 common: Move checkcpu() out of common.h
This function belongs in cpu_func.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:14 -05:00
Simon Glass
b5981474f1 common: Move some CPU functions out of common.h
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
68a6aa85ec common: Move mii_init() function out of common.h
This function belongs in mii.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
1045315df0 common: Move get_ticks() function out of common.h
This function belongs in time.h so move it over and add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
e3107d159c arm: pxa: Drop pxa_wait_ticks()
This function has a similar name to the common wait_ticks(). It is only
used in one place and seems small enough to drop.

Inline it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
6887c5bed9 common: Move some time functions out of common.h
These functions belong in time.h so move them over and add comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
b03e0510d7 common: Move serial functions out of common.h
These functions belong in serial.h so move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
2189d5f1e8 Move strtomhz() to vsprintf.h
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.

Use the vsprintf.h include file explicitly where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:09 -05:00
Simon Glass
3db7110857 crc32: Use the crc.h header for crc functions
Drop inclusion of crc.h in common.h and use the correct header directly
instead.

With this we can drop the conflicting definition in fw_env.h and rely on
the crc.h header, which is already included.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:08 -05:00
Simon Glass
c076e5c9b3 status_led: Tidy up the code style
There are a few whitespace problems with this code. Tidy them up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Simon Glass
9ce2aa1710 Drop CONFIG_SHOW_ACTIVITY
This feature is not enabled by any board. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-02 18:23:06 -05:00
Simon Glass
62f9b65447 common: Move older CPU functions to their own header
These should be moved to driver model, but in the meantime, move them
out of the common header to help reduce its size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Tom Rini
1f3813c2ab Merge branch 'master' of git://git.denx.de/u-boot-mips
- MIPS: remove Micronas VCT boards
2019-12-02 10:53:07 -05:00
Daniel Schwierzeck
2a250ae9b6 MIPS: remove Micronas VCT boards
The deadline for migration to CONFIG_DM is v2020.01. The VCT
baords would need an almost complete rewrite of all drivers to
support driver model.

Unless someone has access to the hardware and volunteers to do the migration,
the board should be scheduled for removal.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2019-11-29 16:18:35 +01:00
Tom Rini
dd38416d6b Merge git://git.denx.de/u-boot-socfpga
- Assorted Gen5 fixes
2019-11-28 07:34:41 -05:00
Tom Rini
089612da33 Merge tag 'mmc-11-27-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc update and some cleanup in ls1021a/mpc83xx code
- mmc tmio sdhi update for hs400
2019-11-28 07:33:45 -05:00
Tom Rini
29061447a0 - Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
 - Correct the eMMC pin configuration on stm32mp157c-ev1
 - Add DFU and SPI-NAND support for stm32mp1 board
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAl3dN0YACgkQ4rK92eCq
 k3WlywgAisVONrdkoC345Kq1vQRcKGYxcWVd0IWkuK3QZ4KrMRQrhEqXhmR7OhWD
 4YrAlgV6FEBTlacfKKsxaL7MJ3VK+h5YLvqoGzZS2Inmrx09v6rOofVTRevmB4Qz
 SlIeUKVBijORmRi31I/WcLdiPgd3RR53wQgAugU3PUpuoUb1Z+sJdOreOkl5qGyZ
 8aRgvG/if8afILXfH/a4IUuPboaVjaC5B20JCzX4M4ks8lHJ3atbtawgj/e41yYv
 Ybq3QudM62g4SvTgJ5/1yqjQ4Oj8dkAY7JyAiXfHa9Kip7s16aBDFklDH7eR9v7F
 IxyoYcFhuPADE7ApdWtij/y/KRS66Q==
 =oVPG
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20191126' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
- Correct the eMMC pin configuration on stm32mp157c-ev1
- Add DFU and SPI-NAND support for stm32mp1 board
2019-11-28 07:33:16 -05:00
Tom Rini
4b39568cfd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- powerpc: Fix DM_MMC related build warnings by adding eSDHC device
  module support for T4240RDB, T2080RDB, T1042D4RDB, T1024RDB, P5040DS,
  P4080DS, P3041DS, P2041RDB, P2020RDB, P1020RDB platforms
2019-11-28 07:32:44 -05:00
Yangbo Lu
1eaffca076 mpc83xx: remove unused clock.h
The clock.h was to define mxc_get_clock() providing clock value
to fsl_esdhc driver. Since fsl_esdhc driver is using global data
gd->arch.sdhc_clk directly now, we can remove this file.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Yangbo Lu
d3eb317ea5 arm: drop eSDHC clock getting in mxc_get_clock() for layerscape
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms,
eSDHC clock getting do not have to use it. It uses global data
gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more
than one eSDHC controllers on SoC, they use same reference clock.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Patrick Delaunay
4d7d0e2e78 ARM: dts: stm32: update eMMC configuration for stm32mp157c-ev1
Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1.
- update slew-rate for pin configuration
- update "vqmmc-supply"
- remove "st,sig-dir"
- add mandatory "pinctrl-names"
- add "mmc-ddr-3_3v"

This patch solve the eMMC detection issue for command "mmc dev 1".

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-11-26 10:11:48 +01:00
Patrick Delaunay
62d620c243 ARM: dts: stm32: DT alignment with kernel v5.4-rc4
Device tree and binding alignment with kernel v5.4-rc4

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-11-26 10:11:48 +01:00
Patrick Delaunay
e07a86b5e3 ARM: dts: stm32: DT alignment with kernel v5.3
Device tree and binding alignment with kernel v5.3
and converted to SPDX.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-11-26 10:11:48 +01:00
Tom Rini
4b19b89ca4 - add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
 - add support for one binary on RPi3/4
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl3a8R4SHG1icnVnZ2Vy
 QHN1c2UuY29tAAoJEC9tfk32wqh+AfQP/iO4qiJWUsY1WgChKl0wZNnkJKViNu6v
 F7zczCIUyI7krdVb3E3PB/ZJwXY/ay1rQeY91cU/9f0Z3yOlsoiwnEfOT/HwwkmD
 KnS6nhisqL0W1yd8sK8XaLOydIFfe05Do1UvF1JhOl3061R81fdruXygkHlgFXiK
 /hrEXLb9l0Zf4XMSD9hQJZiC/K3qeUZV1KsEdSGArjjTj3kivvS++Z0XD1YZsBVs
 rsEl3ZhPeUmzAxmg26IfyJan02NjWY+MyuoSd8QW5kVGsF4WOgvDuBOY1YJ08C/7
 NhLGkub/XhqHVSaMDwiSoX9d2z7ZqTaw7+IZW38+fCMUFAEHiErqMDq+Zfk1DKCd
 WynOzMj6k+Kli+amHQMHuUqIY54XPwpXdn671C7XbQ8xWh7HhWH/sEHP7ekrSV74
 Et7dy5fcleCcrr8EDhdC5iO2fLKhswq4iT0PbnFMtha4jhPqFVHVaAZDacucJ1/V
 JpfYRkLrmEbva3G1emve80tzlDNDxjraX8G6/6trN+F0xjorcbImp64RtRjgdL62
 DwIuba15BGR18LQJY/yHSHT4h3ReEG5qF9vxX+r6vMiFACZbnBPAP/b/REDQ6LWs
 dwW01JQ343dmZiegBQOe98fRDMGhmTd52mAJ/8p60X+byIh5I4XFKCdEdUpSVBpK
 ARrdtg9vtLxv
 =4Z+A
 -----END PGP SIGNATURE-----

Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-boot

- add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
- add support for one binary on RPi3/4
2019-11-25 12:56:27 -05:00
Marek Vasut
a1a9843a29 ARM: socfpga: Unreset NAND in SPL on Gen5
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP
explicitly in the platform code as the denali-spl driver is not aware
of DM at all.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
2007a730ee ARM: socfpga: Add ArriaV ST/SX ID
Add new FPGA ID for ArriaV ST/D3 or SX/B3 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
97a72bc286 ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.

When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba <------- this is in fact a value which is stored in
                            a memory at 0xff200000
=> bridge enable ; md 0xff200000 1
ff200000: 90effe09 <------- this is in fact a value which is stored in
                            a memory at 0xff200010
and so it continues. Issuing a write does lock the system up completely.

This patch opens the FPGA bridges in 'bridge enable' command, the tears
them down again, and then opens them again. This allows these outstanding
transactions to complete and makes this misbehavior go away.

However, it is not entirely clear whether this is the correct solution.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25 13:12:56 +01:00
Marek Vasut
446cf811c5 ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register,
which releases all bridges from reset, instead of putting all bridges
into reset. Fix this by inverting the mask and actually putting the
bridges into reset.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-25 13:12:55 +01:00
Yinbo Zhu
c44d05d97b arch: powerpc: add eSDHC node to t4240 dts
Add eSDHC node to t4240 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
3f8f668d8c arch: powerpc: add eSDHC node to t104x dts
Add eSDHC node to t104x dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
d2c398b75f arch: powerpc: add eSDHC node to t102x dts
Add eSDHC node to t102x dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
428e7a1da6 arch: powerpc: add eSDHC node to p5040 dts
Add eSDHC node to p5040 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
9d05cd2ae9 arch: powerpc: add eSDHC node to p4080 dts
Add eSDHC node to p4080 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
dfeb70c182 arch: powerpc: add eSDHC node to p3041 dts
Add eSDHC node to p3041 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:27 +05:30
Yinbo Zhu
067e09f23f arch: powerpc: add eSDHC node to p2041 dts
Add eSDHC node to p2041 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Yinbo Zhu
e126363dc7 arch: powerpc: add eSDHC node to p2020 dts
Add eSDHC node to p2020 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Yinbo Zhu
b73d5379c5 arch: powerpc: add eSDHC node to p1020 dts
Add eSDHC node to p1020 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25 11:54:26 +05:30
Matthias Brugger
5694090670 ARM: defconfig: add unified config for RPi3 and RPi4
Provide a defconfig which allows us to boot Raspberrry Pi 4
and Raspberry Pi 3 Model B/B+
Instead of using the embedded DTB as done in RPi3 we use the
devicetree provided by the firmware.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:28 +01:00
Matthias Brugger
917a1e9a78 ARM: bcm283x: Set memory map at run-time
For bcm283x based on arm64 we also have to change the mm_region.
Add assign this in mach_cpu_init() so we can create now one binary
for RPi3 and RPi4.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:28 +01:00
Matthias Brugger
dd47ca7873 ARM: bcm283x: Set rpi_bcm283x_base at run-time
As part of the effort to create one binary for several bcm83x SoCs
we read the IO base address from device-tree.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
8e3361c88a ARM: bcm283x: Move BCM283x_BASE to a global variable
We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
5051377a0b arm: dts: bcm283x: Rename U-Boot file
Rename the file bcm283x-uboot.dtsi so that it get
automatically include through the scripts/Makefile.lib
using $(CONFIG_SYS_SOC))-u-boot.dtsi

Without this uarts and pincontroller miss the property dm-pre-reloc
and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails
as the pins are not set correctly.
As a result the U-Boot banner isn't shown on boot.

Before commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we included bcm283x-uboot.dtsi directly in the device-tree file.
Which got deleted by the metioned commit.
This is a much robuster solution.

Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
89e47e8eb6 fdt: fix bcm283x dm-pre-reloc definitions
In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we deleted the label for the node soc from bcm283x.dtsi

As we don't need to add the property dm-pre-reloc to the soc node,
we can delete it from bcm283x-uboot.dtsi

Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Tom Rini
9a0cbae22a Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean vid/pid in Kconfig and add fastboot for rk3399
- add 'u-boot, spl-fifo-mode' for mmc
- Use FIT generator for rk3229 optee and rk3368 ATF
- fan53555: add support for Silergy SYR82X and SYR83X
2019-11-23 20:50:11 -05:00
Heinrich Schuchardt
16540d07fd arm: fix -march for ARM11
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html

ARM11 is an armv6 implementation. So change the architecture flag for the
compiler to armv6 for ARM11.

Suggested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-11-23 14:53:48 -05:00
Heiko Stuebner
8019d32c47 rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evb
As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.

The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.

There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-11-23 23:41:44 +08:00
Jagan Teki
c618bb0042 rockchip: Setup dwc3_device (for non-dm gadgets)
Setup dwc3_device structure for non-dm gadgets, which is used
in rk3399 platforms.

dwc3_device would have basic regbase, dr_mode, high speed
and 16-bit UTMI+ etc.

Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix to use CONFIG_USB_DWC3_GADGET instead of CONFIG_USB_DWC3)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 23:41:44 +08:00
Kever Yang
65325fba5a rockchip: Convert to use FIT generator for optee
Use generator script so that we can use environment for TEE source.
$TEE for tee.bin, and if file not exist, the script can report a warning,
and meke the build success without a error.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Tom Rini
47b48fe186 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Assorted fixes
2019-11-22 10:41:46 -05:00
Tom Rini
71d96eb99e Merge branch 'master' of git://git.denx.de/u-boot-sh
- Assorted Gen3 fixes
2019-11-22 10:24:14 -05:00
Ooi, Joyce
0c14bb5ad3 arm: socfpga: stratix10: Add alias for gmac0 in S10 dts
Add 'ethernet0' as alias for 'gmac0' in S10 device tree.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-22 03:08:12 +01:00
Ooi, Joyce
7dad444c76 arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay which was needed in
Arria10.

Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-22 03:08:12 +01:00
Tom Rini
a09fea1d28 env: Finish migration of common ENV options
- In ARMv8 NXP Layerscape platforms we also need to make use of
  CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so.
- On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define
  to 0.
- Add Kconfig entry for ENV_ADDR.
- Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it.
- Add ENV_xxx_REDUND options that depend on their primary option and
  SYS_REDUNDAND_ENVIRONMENT
- On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR
  for the pre-main-U-Boot environment location.
- On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but
  rather it being non-zero, as it will now be zero by default.
- Rework the env_offset absolute in env/embedded.o to not use
  CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within
  ENV_IS_IN_FLASH.
- Migrate all platforms.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: uboot-stm32@st-md-mailman.stormreply.com
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20 18:32:09 -05:00
Simon Goldschmidt
26fb85f4ab socfpga: fix include guard in misc.h (arch vs. global)
The file arch/arm/mach-socfpga/include/mach/misc.h used the same include
guard as the global include/misc.h.

Fix this by giving the arch file an arch prefix.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-20 22:32:00 +01:00
Ley Foon Tan
9184590d9a arm: dts: Stratix10: Fix memory node address and size cells
Add #address-cells and #size-cells to memory node to fix incorrect memory
size decoding in recent Uboot version.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-20 22:32:00 +01:00
Tom Rini
ad38de2093 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- Fix CONFIG_AHCI related build warning for P2041, P3041, P5040, T102x,
  T104x, T4240 platforms
2019-11-20 15:38:51 -05:00
Heinrich Schuchardt
d47a774680 arm: arm11: allow unaligned memory access
The UEFI spec mandates that unaligned memory access should be enabled if
supported by the CPU architecture.

This patch implements the function unaligned_access() to set the enable
unaligned data support flag and to clear the aligned flag in the system
control register (SCTLR). It is called when UEFI related commands like
bootefi are invoked.

Reported-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Tested-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Tested-by: Guillaume Gardet <Guillaume.Gardet@arm.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-11-19 12:10:22 +01:00
Peng Ma
037e1084d9 powerpc: t4240: dts: Add Sata DT nodes
This patch is to add sata node for T4240 platform

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
5023917db2 powerpc: t104x: dts: Add Sata DT nodes
This patch is to add sata node for T104x platform

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
e68ed561bc powerpc: t102x: dts: Add Sata DT nodes
This patch is to add sata node for T102x platform

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
5799a38ae3 powerpc: p5040: dts: Add Sata DT nodes
This patch is to add sata node for P5040 platform

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
e71499aada powerpc: p3041: dts: Add Sata DT nodes
This patch is to add sata node for P3041 platform

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
48d8910378 powerpc: p2041: dts: Add Sata DT nodes
This patch is to add sata node for P2041 platform

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
e08b5b1465 ata: fsl_sata: Add DM support for Freescale PowerPC SATA driver
Add DM support for Freescale PowerPC sata driver used for PowerPC T series
SoCs,

CONFIG_BLK needs to be enabled on these platforms. It adds the SATA
controller as AHCI device, which is strictly speaking not correct,
as the controller is not AHCI compatible, But the U-Boot AHCI uclass
interface enables the usage of this DM driver,

Also fix below warning while PowerPC T series boards compilation,

===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Tom Rini
fffb826ea0 - fix i.MX6ULL evk black screen observed while reboot stress tests
- remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree
   differences between Linux and U-Boot for stm32mp1 platform
 -----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXdJyOg4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXOmuAJ9lF7GyPpv0vZNX1V4UV2EyyOOdbwCfQzHu3Xo+
 3VWLV9ZHkVMlfnGbbx0=
 =+YuG
 -----END PGP SIGNATURE-----

Merge tag 'video-for-v2020.01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- fix i.MX6ULL evk black screen observed while reboot stress tests
- remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree
  differences between Linux and U-Boot for stm32mp1 platform
2019-11-18 10:48:29 -05:00
Tom Rini
d64efd920e Merge tag 'u-boot-rockchip-20191118' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip SoC: PX30, RK3308
- Add and migrate to use common dram driver: PX30, RK3328, RK3399
- Add rk3399 board Tinker-s support
- Board config update for Rock960, Rockpro64
2019-11-17 21:15:57 -05:00
Tom Rini
fd8adc33b8 Add OP-TEE test swuit
Fix patman cc_file output
 Minor sandbox/pinctrl changes
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAl3NiIMRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreYC2gf8DE+un/xHxyRwxCdnWuDI4dhC0Reffp3z
 5cyYv10du8t5fAkqbNHVodx/nG+P339x3Dvz8+4wJaJXJH9tdm04q28uE/iG89T1
 yf6pHRmeyp8FoveeScMAtx7OFgyG2l93K/sqhEQQKvnNadMDXjJPcmixgU4igNha
 JaPb6n4Hd04tSHyDgfeYz6kXW5Bxlp37t0UwKHSLfYMk4CH0hsydRV4FDoGRFups
 HAhT43B8b2Ml1MfQG+jgcrLfwGCRr+a6PamzmR1KW/LxhiVLl+XU8hfCBXnO9CXy
 Em/aJasNA6Wl4GaXy46UjM6xeUL2irENU5NvW5F+gTJ31tuoj+Movg==
 =y/5J
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-14nov19' of git://git.denx.de/u-boot-dm

Add OP-TEE test swuit
Fix patman cc_file output
Minor sandbox/pinctrl changes
2019-11-17 21:15:23 -05:00
Michael Trimarchi
59b01eb7a1 rockchip: dts: tinker: Add tinker-s board support
Support tinker-s board. The board is equivalent of tinker board
except of emmc.

TODO:
- support of usb current burst when the board is powered from pc

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 18:51:25 +08:00
Michael Trimarchi
b40abe3369 rockchip: dts: tinker: Move u-boot dmc initialization to specific section
dmc is used to initialize the memory controller. It's needed by
u-boot. Move it in the specific section

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 18:51:25 +08:00
Thomas Hebb
64eff47c78 rockchip: imply instead of selecting SPL_SYS_MALLOC_SIMPLE
We shouldn't force which allocator the SPL uses, since there's no
platform requirement for one over the other: in fact, we currently allow
selection of the TPL allocator but not the SPL one!

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 18:51:25 +08:00
Thomas Hebb
857d638ca6 rockchip: allow DRAM init in SPL
The common SPL removed SoC-specific code for RK3399's SPL and in the
process caused the previously-unconditional DRAM initialization in
board_init_f() to only happen when compiling a configuration that does not
support TPL, meaning DRAM never gets initialized if TPL is supported but
disabled.

Fix this by omitting the DRAM init in SPL only when we are configured to
also build a TPL. This fixes custom configurations that have disabled
TPL, and it should also unbreak the "ficus-rk3399", "rock960-rk3399",
and "chromebook_bob" defconfigs, although since I don't have any of
those devices I can't confirm they're broken now.

Fixes: b7abef2ecb ("rockchip: rk3399: Migrate to use common spl board file")

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 18:54:29 +08:00
Thomas Hebb
220697a317 rockchip: SPL: fix ordering of DRAM init
The common SPL code reordered the DRAM initialization before
rockchip_stimer_init(), which as far as I can tell causes the RK3399 to
lock up completely.

Fix this issue in the common code by putting the DRAM init back after
timer init. I have only tested this on the RK3399, but it wouldn't make
any sense for the timer init to require DRAM be set up on any system.

Fixes: b7abef2ecb ("rockchip: rk3399: Migrate to use common spl board file")

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 18:51:25 +08:00
Andy Yan
208b8cd646 rockchip: rk3308: Add support for ROC-RK3308-CC board
ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Andy Yan
9ce3de1b18 rockchip: rk3308: Add dts for ROC-RK3308-CC
Add dts file for ROC-RK3308-CC from firefly.

Sync form linux rockchip for v5.5-armsoc/dts64:
"arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc"
(sha1: 4403e1237be3af0977aa23ef399e3496316317a0)

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Andy Yan
9e3de722e4 board: rockchip: Add rk3308 evb support
Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Andy Yan
22dcd28150 arm: dts: rockchip: Add dts for rk3308 evb
Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Andy Yan
f1a225229a arm: rockchip: Add RK3308 SOC support
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Elaine Zhang
bbda2ed584 rockchip: clk: pll: add common pll setting funcs
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
7acd030210 rockchip: rk3399: orangepi: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
4d273ff304 rockchip: rk3399: khadas-edge: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
8dda40ec51 rockchip: rk3399: rock-pi4: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
f9f68ea747 arm64: dts: rk3399-rock960: add vdd_log and its init value
Add vdd_log node according to rock960 schematic V13.
This patch affect two boards:
- Rock960 Model A
- Ficus

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-11-17 17:22:53 +08:00
Peter Robinson
267b6adf63 rockchip: dts: rk3399-firefly: move u-boot, spl-boot-order to to the u-boot.dtsi
The u-boot specific device tree directives should be in u-boot.dtsi

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Peter Robinson
e7505d06bd rockchip: dts: rk3399-evb: move u-boot, spl-boot-order to to the u-boot.dtsi
The u-boot specific device tree directives should be in u-boot.dtsi

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Peter Robinson
f459e23ec0 rockchip: dts: rk3399: move the u-boot, dm-pre-reloc to the u-boot.dtsi
The u-boot specific pieces in the dts files should be in u-boot.dtsi
not the main files, this allows easier sync with upstream. The
rk3399.dtsi has a mix of both so move them all for consistency.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix with missing pmugrf)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Vasily Khoruzhick
de43ca7e3e rockchip: rk3399: split rockpro64 out of evb_rk3399
rockpro64 needs to setup I/O domains in order for USB to work in u-boot.
Since we currently don't have a driver to do that, split it into its own
board file and initialize I/O domains here.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
a04f6fd17f rockchip: clk: rv1108: remove duplicate reset init
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.

So we can get rid of the open-coded reset init and just fix
the correct cru reference.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Soeren Moch
f210cbc1f3 arm: dts: rk3399-rockpro64: slightly increase center voltage
The rk3399 VD_CENTER voltage domain is not subject to dynamic voltage
scaling. So the regulator reset voltage of 0.9V is used on this board.
Let u-boot initialize the center voltage to 0.95V as it is done for the
VD_LOGIC domain. This avoids instability and occasional linux kernel
Opses on this board.

Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Soeren Moch
5824ad3453 arm: dts: rk3399-rockpro64: sync dts from linux kernel
The most important change for u-boot is the fix for the vdd-log pwm
voltage regulator to avoid overvoltage for the VD_LOGIC power domain.

Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Jagan Teki
37f4e531d7 arm: dts: rk3399-roc-pc: Sync latest dts changes from Linux
Few important regulator power rails fixes are available in
linux-next, so sync them same.

Here is the last commit details:
commit <9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326> ("arm64: dts:
rockchip: Fix roc-rk3399-pc regulator input rails")

Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
17224b325f rockchip: Init driver otg_data for rk3288 usb phy
RK3288 needs to init the otg_data in board level to make the phy driver
work.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
e76943ca6f rockchip: usb: Migrate to use ofnode
Migrate to use ofnode_* instead of fdt_* so that we may able to use live
dt for usb udc driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
e9ccb2f526 rockchip: add px30 architecture core
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:24 +08:00
Heiko Stuebner
537b1a2774 rockchip: add px30 devicetrees
Add px30 related devicetrees synced from the Linux kernel.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:20 +08:00
Heiko Stuebner
e61350a5f5 rockchip: misc: read cpuid either from efuse or otp
Newer Rockchip socs use a different ip block to handle one-time-
programmable memory, so depending on what got enabled get the cpuid
from either source.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:18 +08:00
Kever Yang
d49a526750 rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:07 +08:00
Heiko Stuebner
46281a76be rockchip: add core px30 headers
Add headers needed by the upcoming px30 support, including two
new dt-binding headers taken from the Linux kernel.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:00 +08:00
Heiko Stuebner
22b7b86005 spl: separate SPL_FRAMEWORK config for spl and tpl
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.

Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00