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3 commits

Author SHA1 Message Date
Xu Ziyuan
7a25a63c13 rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO 
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
 2017-05-10 13:37:21 -06:00
Heiko Stübner
f785357073 rockchip: clk: rk3188: Allow configuration of the armclk 
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
 2017-04-04 20:01:57 -06:00
Heiko Stübner
dcdd32788a rockchip: rk3188: Add clock driver 
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
 2017-03-16 16:03:45 -06:00