Commit graph

15 commits

Author SHA1 Message Date
Dalon Westergreen
6bd041f00d arm: socfpga: add cyclone5 based de10-nano board
Add support for the Terasic DE10-Nano board.  The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-25 12:46:44 +02:00
Dinh Nguyen
6fa0d34572 MAINTAINERS: socfpga: update email address for Dinh Nguyen
With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-12-06 01:45:58 +01:00
Anatolij Gustschin
e9c847c363 socfpga: add support for Terasic DE1-SoC board
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
2016-12-06 01:45:56 +01:00
Chin Liang See
bdef7876ad arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:12 +02:00
Chin Liang See
13022d852d arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:11 +02:00
Marek Vasut
4d74c02724 arm: socfpga: sockit: Use more relaxed DRAM timings
The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-10 17:19:48 +02:00
Marek Vasut
dbd6fcfbe2 arm: socfpga: Drop the board boilerplate
Drop all the common board code, since it is not completely useless.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut
225217da28 arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:51 +01:00
Marek Vasut
1f5f187172 arm: socfpga: sockit: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:50 +01:00
Marek Vasut
5df93c5564 arm: socfpga: de0_nano: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:50 +01:00
Marek Vasut
5d5716eebc usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.

The rename is done automatically:
	$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
		`git grep "s3c_udc\.h" | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:41 +01:00
Marek Vasut
a4bb9b3636 usb: s3c-otg: Rename s3c_udc_probe() function
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.

The rename is done automatically:
	$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
		`git grep s3c_udc_probe | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
c0982871df usb: s3c-otg: Rename struct s3c_plat_otg_data
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.

The rename is done automatically:
	$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
		`git grep s3c_plat_otg_data | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Dinh Nguyen
55c7a765f6 arm: socfpga: Add support for the Terasic DE-0 Atlas board
Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV
based board. The board can boot from SD/MMC. Ethernet is also supported.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-04 11:54:21 +02:00
Marek Vasut
952caa289e arm: socfpga: Add support for Terasic SoCkit board
Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-09-04 11:54:21 +02:00