The variables gpll_init_cfg and apll_init_cfg are unused in this file,
remove them.
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The variable syndrome_codes is only used when DEBUG is define, add #if
guards around it in the same style as the rest of the file.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
On the controlcenterd_36BIT_SDCARD config we get a warning about
prg_stage1_prepare being unused. Move the declaration closer to usage
and hide under the existing #if tests.
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that we can specify DT nodes that can be used in spl, mark
all necessary nodes as u-boot,dm-spl.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we can specify DT nodes that can be used in spl, mark
all necessary nodes as u-boot,dm-spl.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
It has been observed that between PG1.0 and PG2.0/2.1 depending on
which device we boot from, we may see a different value here than is
documented in the TRM. Update the values for NAND and MMC1 based on
real life usage on each revision.
Signed-off-by: Tom Rini <trini@konsulko.com>
In armada_37xx_gpiochip_register, the return value of fdtdec_get_bool
should be true when gpio-controller is found; current codes makes a
wrong inverse return value judgement, this patch fixes it.
Signed-off-by: Ken Ma <make@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.
Signed-off-by: Ken Ma <make@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
As all x86 boards have been switched over to use DM USB, remove
CONFIG_USB_MAX_CONTROLLER_COUNT which is not used by DM USB.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
GPIO bank E pin 8 & 9 are used to control the on-board two USB ports
VBUS on/off. Let's configure them in the misc_init_r().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
I would like to help Stefano Babic as a co-maintainer of
U-Boot i.MX.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
On ARCH_SUNXI we've been selecting these targets for a long time if
SUPPORT_SPL is set. However, Lichee Pi Zero is the first platform we've
added that does support SPL but does not build SPL and has exposed a
latent bug. Both of these symbols depend on SPL not SUPPORT_SPL, so we
need to update our select here otherwise we get a Kconfig warning.
Fixes: f02abb0608 ("sunxi: add support for Lichee Pi Zero")
Signed-off-by: Tom Rini <trini@konsulko.com>
The commit "fb82fe385173 configs: Resync defconfigs" resynced all config
files. This exposed two latent issues with the Gen3 boards in that we
had not been setting CONFIG_DEFAULT_FDT_FILE correctly and had not been
setting CONFIG_CMD_MMC. Fix both of these.
Fixes: fb82fe3851 ("configs: Resync defconfigs")
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
endian.h on FreeBSD system exist in sys/ subdirectory.
FreeBSD already have a fls function defined in strings.h which is included
in string.h if __BSD_VISIBLE is defined, as a check for this.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
The driver currently does not reset bit 5 of the hostctl register even if
the MMC stack requests it. Then means that once a bus width of 8 is
selected it is not possible to change it back to 1. This breaks
'mmc rescan' which needs to start off with a bus width of 1.
The problem was surfaced by enabling CONFIG_DM_MMC_OPS on tegra. Without
this option the MMC stack fully reinits the driver on a 'mmc rescan'.
But with this option driver model does not re-probe a driver once it has
been probed once.
Fix the driver to honour the request.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Chubb <peter.chubb@data61.csiro.au>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM,
64MB dual-parallel QSPI NOR flash and clock sources.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the
associated topic_miamiplus.h header obsolete, so remove that as well.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reuse invoke_smc() routine which is already defined
instead of duplicating same at multiple places.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define routines of mmio write and read functionalities
for zynqmp platform.
Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.
Also make invoke_smc as global so that it can be reused in
multile places where ever possible.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add Kconfig option for ddr init as this might be required
in cases like ddr less systems where we want to skip ddrc
init and this option is useful for it.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Silicon v1 didn't support SD boot mode with level shifter.
Because system can't boot any error message is not shown
that's why comment is just a record if someone tries to debug it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
psu_init* contain sleep.h header which is not present in u-boot.
Instead of keep comment sleep.h in psu_init* it is easier to add empty
file which is included.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Drop include of netdev.h as it's a SATA driver not a network driver.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Decrease malloc size to 1MB from 256MB. Huge malloc
space is adding huge delay in mem_malloc_init() because
we are enabling CONFIG_SYS_MALLOC_CLEAR_ON_INIT
which clear the whole malloc space.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The boot_device argument to spl_boot_mode was massively added without
actually modifying the existing functions.
This commit actually makes use of the handed value, which is the same.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When enabling both SDHCI controllers, spl_mmc.c would actually choose
device sdhci0 even if booted from sdhci1 (boot_device). This is because
spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in
order to return index 1 instead of 0.
The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c
So the key to properly enabling both controllers as boot sources is
defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's
include/configs/*.h.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Adding more targets to repository requires some additional
changes not simply just adding config file, defconfig and dts.
This patch makes this process easier by building only
particular DTB which is selected via defconfig
that Makefile doesn't need to contain all dts files in the repository.
Reported-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CPU_RELEASE_ADDR is used only when CONFIG_ARMV8_MULTIENTRY
is enabled. ZynqMP is running ATF which takes care about this
that's why no need to have this macro.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make do_usb_mass_storage() static to fix the following sparse
warning:
cmd/usb_mass_storage.c:136:5: warning: symbol 'do_usb_mass_storage' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Use NULL for pointer to fix the following sparse warning:
cmd/usb_mass_storage.c:47:15: warning: Using plain integer as NULL pointer
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
With gcc-6 and later we see warnings that at91sam9263_udc_caps and
at91rm9200_udc_caps are unused.
Fixes: 620197670a ("usb: gadget: at91_udc: add at91_udc into U-Boot")
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
Current implementation doesn't allow utilization of platform-specific
reads and writes.
But some arches or platforms may want to use their accessors that do
some extra work like adding barriers for data serialization etc.
Interesting enough OHCI accessors already do that so just aligning
EHCI to it now.
This is a resend of http://patchwork.ozlabs.org/patch/726714/
Back in the day this patch broke some PPC and Sandbox boards
as they we missing inclusion of "asm/io.h". Those missing items were
fixed with:
1) http://patchwork.ozlabs.org/patch/751397/
2) http://patchwork.ozlabs.org/patch/771099/
So now it should be safe to apply this patch.
FWIW TravisCI builds everything with all 3 patches in place,
see https://travis-ci.org/abrodkin/u-boot/builds/239563813
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
In current code, after running the command of "usb start", the controller
will keep in otg mode and can't switch to host mode if not support
SNP/SRP capability. So add the property of "hnp-srp-disable" in the DTS
to config the contrller work in force mode of host.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
