Commit graph

68568 commits

Author SHA1 Message Date
Alper Nebi Yasak
1e4687aa47 binman: Use target-specific tools when cross-compiling
Currently, binman always runs the compile tools like cc, objcopy, strip,
etc. using their literal name. Instead, this patch makes it use the
target-specific versions by default, derived from the tool-specific
environment variables (CC, OBJCOPY, STRIP, etc.) or from the
CROSS_COMPILE environment variable.

For example, the u-boot-elf etype directly uses 'strip'. Trying to run
the tests with 'CROSS_COMPILE=i686-linux-gnu- binman test' on an arm64
host results in the '097_elf_strip.dts' test to fail as the arm64
version of 'strip' can't understand the format of the x86 ELF file.

This also adjusts some command.Output() calls that caused test errors or
failures to use the target versions of the tools they call. After this,
patch, an arm64 host can run all tests with no errors or failures using
a correct CROSS_COMPILE value.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
5ac7687827 binman: Support cross-compiling test files to x86
These test files are currently "intended for use on x86 hosts", but most
of the tests using them can still pass when cross-compiled to x86 on an
arm64 host.

This patch enables non-x86 hosts to run the tests by specifying a
cross-compiler via CROSS_COMPILE. The list of variables it sets is taken
from the top-level Makefile. It would be possible to automatically set
an x86 cross-compiler with a few blocks like:

    ifneq ($(shell i386-linux-gnu-gcc --version 2> /dev/null),)
    CROSS_COMPILE = i386-linux-gnu-
    endif

But it wouldn't propagate to the binman process calling this Makefile,
so it's better just raise an error and expect 'binman test' to be run
with a correct CROSS_COMPILE.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Heinrich Schuchardt
36da81e0c1 dm: syscon: typo alerady
* Fix typo: %s/alerady/already/.
* Add missing 'the'.
* Reformat a comment.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:54:13 -06:00
Alper Nebi Yasak
76de29fc4f buildman: Use git worktrees instead of git clones when possible
This patch makes buildman create linked working trees instead of clones
of the source repository, but keeps updating the older clones of the
repository that might already exist. These worktrees share "everything
except working directory specific files such as HEAD, index, etc." with
the source repository. See the git-worktree(1) manual page for more
information.

If git-worktree isn't available, silently falls back to cloning the
repository.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
f5bbd9a3a6 sunxi: Drop the FIT-generator script
This file is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
cfa3db602c sunxi: Convert 64-bit boards to use binman
At present 64-bit sunxi boards use the Makefile to create a FIT, using
USE_SPL_FIT_GENERATOR. This is deprecated.

Update sunxi to use binman instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22 12:50:43 -06:00
Simon Glass
bd4d0dcb27 Makefile: Support missing external blobs always
At present binman warns about missing external blobs only when the
BUILD_ROM is defined. Enable this behaviour always, since many boards
are starting to use these (e.g. ARM Trusted Firmware's BL31).

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
6cf9953bfb binman: Support generating FITs with multiple dtbs
In some cases it is useful to generate a FIT which has a number of DTB
images, selectable by configuration. Add support for this in binman,
using a simple iterator and string substitution.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
dc2f81a2c8 binman: Add support for ATF BL31
Add an entry for ARM Trusted Firmware's 'BL31' payload, which is the
device's main firmware. Typically this is U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
8795898a53 binman: Move 'external' support into base class
At present we have an Entry_blob_ext which implement a blob which holds an
external binary. We need to support other entry types that hold external
binaries, e.g. Entry_blob_named_by_arg. Move the support into the base
Entry class to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
211cfa503f libfdt: Detected out-of-space with fdt_finish()
At present the Python sequential-write interface can produce an error when
it calls fdt_finish(), since this needs to add a terminating tag to the
end of the struct section.

Fix this by automatically expanding the buffer if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
e9d336d866 binman: Fix up a few missing comments
Tidy up a few test functions which lack argument comments. Rename one that
has the same name as a different test.

Also fix up the comment for PrepareImagesAndDtbs().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
3decfa3a87 binman: Allow entry args to be required
If an entry argument is needed by an entry but the entry argument is not
present, then a strange error can occur when trying to read the file.

Fix this by allowing arguments to be required. Select this option for the
cros-ec-rw entry. If a filename is provided in the node, allow that to be
used.

Also tidy up a few related tests to make the error string easier to find,
and fully ignore unused return values.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Walter Lozano
dc447b6b3f core: improve of_match_ptr with OF_PLATDATA
Currently of_match_ptr is used to avoid referencing compatible strings
when OF_CONTROL is not enabled. This behaviour could be improved by
taking into account also OF_PLATDATA, as when this configuration is
enabled the compatible strings are not used at all.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
2b522f1e79 tools: Drop unnecessary use of __file__
There are few places where the path of the current modules is calculated
but not used. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Simon Glass
9fbfaba0a7 binman: Use pkg_resources to find resources
At present we look for resources based on the path of the Python module
that wants them. Instead we should use Python's pkg_resources feature
which is designed for this purpose.

Update binman to use this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Alper Nebi Yasak
fe05701b05 binman: Build FIT image subentries with the section etype
When reading subentries of each image, the FIT entry type directly
concatenates their contents without padding them according to their
offset, size, align, align-size, align-end, pad-before, pad-after
properties.

This patch makes sure these properties are respected by offloading this
image-data building to the section etype, where each subnode of the
"images" node is processed as a section. Alignments and offsets are
respective to the beginning of each image. For example, the following
fragment can end up having "u-boot-spl" start at 0x88 within the final
FIT binary, while "u-boot" would then end up starting at e.g. 0x20088.

	fit {
		description = "example";

		images {
			kernel-1 {
				description = "U-Boot with SPL";
				type = "kernel";
				arch = "arm64";
				os = "linux";
				compression = "none";

				u-boot-spl {
				};
				u-boot {
					align = <0x10000>;
				};
			};
		};
	}

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reinstate check in testPadInSections(), squash in
   "binman: Allow FIT binaries to have missing external blobs"
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2020-09-22 12:50:43 -06:00
Alper Nebi Yasak
3fdeb14d95 binman: Respect pad-before property of section subentries
Other relevant properties (pad-after, offset, size, align, align-size,
align-end) already work since Pack() sets correct ranges for subentries'
data (.offset, .size variables), but some padding here is necessary to
align the data within this range to match the pad-before property.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Alper Nebi Yasak
8001d0b162 binman: Ignore hash*, signature* nodes in sections
Switch to str.startswith for matching like the FIT etype does since the
current version doesn't ignore 'hash-1', 'hash-2', etc.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 12:50:43 -06:00
Chris Packham
dc8368b7ee configs: powerpc: Don't set CONFIG_ENV_ADDR for QorIQ SPIFLASH
Setting CONFIG_ENV_ADDR to something other than 0 stops gd->env_addr
from being allocated dynamically. When the environment is in SPI we need
it to be allocated as we can't use a direct memory mapped address.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2020-09-22 11:26:19 -04:00
Heinrich Schuchardt
643b5e7ea3 disk: typo Terra Bytes
512 * 2^32 bytes equals 2 tebibytes.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:26:19 -04:00
Heinrich Schuchardt
4061191727 doc/build/gcc.rst: add missing apt-get *install*
The install command is missing for an apt-get command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-09-22 11:05:32 -04:00
Rasmus Villemoes
24e8c0e3b3 gpio/mpc83xx_spisel_boot.c: include log.h
Fix build failure, it used to get this implicitly through common.h
until f7ae49fc4f (common: Drop log.h from common header).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-09-22 11:05:32 -04:00
Rasmus Villemoes
10a6aa963c spi: mpc8xxx_spi.c: fix cs activate/deactivate
Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke,
I'm guessing due to this hunk

@@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
        if (ret)
                return ret;

+       /* combine the requested flags (for IN/OUT) and the descriptor flags */
+       flags |= desc->flags;
        ret = _dm_gpio_set_dir_flags(desc, flags);

from commit 695e5fd546 ("gpio: update dir_flags management"). But
the blame is mostly on the driver itself which seems rather confused:
The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in
each activate/deactivate, dm_gpio_set_dir_flags() is called with
merely GPIOD_IS_OUT, and then the driver call set_value(0) for
activate.

That used to work, but with the above hunk, the ACTIVE_LOW setting
from the request becomes persistent, so the gpio driver ends up being
asked to set the value to 1 in mpc8xxx_spi_cs_activate().

So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate
functions, and use a value of 1 to mean "logically enabled".

Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the
request and make it up to the list of gpio cs in DT to indicate
whether that CS is enabled when driven low (as is of course usually
the case), but that requires changing
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't
have that hardware to test on. I have, however, tested our
own (mpc8309-based) hardware with this change, and I have also tested
that removing the GPIOD_ACTIVE_LOW from the request and updating our
DT as

-                       gpios = <&spisel 0 0>;
+                       gpios = <&spisel 0 GPIO_ACTIVE_LOW>;

still works.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-09-22 11:05:32 -04:00
Edgar E. Iglesias
28c851f128 arm64: Add support for larger PIE U-Boot
Linking a U-Boot larger than 1MB fails with PIE enabled:
u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
defined in .bss_start section in u-boot.

This extends the supported range by using adrp & add to load symbols
early while starting up.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Edgar E. Iglesias
04d13b5d09 arm64: Trap PIE builds early if load address is not 4K aligned
PIE requires a 4K aligned load address. If this is not met, trap
the startup sequence in a WFI loop rather than running into obscure
failures.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: André Przywara <andre.przywara@arm.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Edgar E. Iglesias
11f4fbf0d4 arm64: Mention 4K aligned load addresses in the PIE Kconfig help
Mention the requirement of 4K aligned load addresses in the
help section for the POSITION_INDEPENDENT option.

Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22 12:47:28 +02:00
Eugen Hristev
919c4f3639 ARM: at91: common: guard ATMEL_PIT code by ifdef
Atmel PIT timer is not available for next products that
have another timer hardware block.
To be able to use the common at91 code, guard the code that uses PIT
by ifdefs.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-22 11:27:18 +03:00
Eugen Hristev
68d3ec599e board: atmel: common: introduce at91_set_eth1addr for second interface
We already have a function to retrieve the mac address from one EEPROM.
For boards with a second Ethernet interface, however, we would
require another EEPROM with a second unique MAC address.
Introduce at91_set_eth1addr which will look for a second EEPROM
and set the 'eth1addr' variable with the obtained MAC address.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
6a6fe3ed4d clk: at91: sama7g5: add clock support
Add clock support for SAMA7G5.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
7b7e226739 clk: at91: pmc: add generic clock ops
Add generic clock ops to be used by every AT91 PMC driver
built on top of CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
36a9630fcb clk: at91: clk-generic: add driver compatible with ccf
Add clk-generic driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
f89268e468 clk: at91: clk-peripheral: add driver compatible with ccf
Add clk-peripheral compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
16502bfa7c clk: at91: clk-system: add driver compatible with ccf
Add clk-system driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
2a1a579bde clk: at91: clk-programmable: add driver compatible with ccf
Add clk-programmable driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
0341733570 clk: at91: clk-utmi: add support for sama7g5
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
ad4d39a964 clk: at91: clk-utmi: add driver compatible with ccf
Add clk-utmi driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
dd4d19ddfb clk: at91: clk-master: add support for sama7g5
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
b4c4e18dbd clk: at91: clk-master: add driver compatible with ccf
Add clk-master driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
e6547a6d0c clk: at91: sam9x60-pll: add driver compatible with ccf
Add sam9x60-pll driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
f1218f0b4f clk: at91: clk-main: add driver compatible with ccf
Add clk-main driver compatible with common clock framework.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
e9885aa7cc clk: at91: sckc: add driver compatible with ccf
Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
653bcce408 clk: at91: move clock code to compat.c
Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
5d729f9629 clk: at91: pmc: add helpers for clock drivers
Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
643966a8fa clk: at91: add pre-requisite headers for AT91 clock architecture
Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
b364134f87 clk: get clock pointer before proceeding
clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each clock driver has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree is a clock registered with clk_register()). In this
case the subsequent operations like dev_get_clk_ptr() on clocks
retrieved by clk_get_by_indexed_prop() will fail. For this, get the
pointer to the proper clock registered (with clk_register()) using
clk_get_by_id() before proceeding.

Fixes: 1d7993d1d0 ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
9a5d59dfc6 clk: do not disable clock if it is critical
Do not disable clock if it is a critical one.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
4d139f3838 clk: bind clk to new parent device
Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
cfecbaf4e7 dm: core: add support for device re-parenting
In common clock framework the relation b/w parent and child clocks is
determined based on the udevice parent/child information. A clock
parent could be changed based on devices needs. In case this is happen
the functionalities for clock who's parent is changed are broken. Add
a function that reparent a device. This will be used in clk-uclass.c
to reparent a clock device.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00
Claudiu Beznea
b04da9fcf7 clk: check hw and hw->dev before dereference it
Check hw and hw->dev before dereference it.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-22 11:27:18 +03:00