Commit graph

13 commits

Author SHA1 Message Date
Masami Hiramatsu
99a2bd65f1 Revert "configs: synquacer: Make U-Boot binary position independent"
This reverts commit f7e16bb0c5, since
the U-Boot doesn't boot if it is booted directly from SPI-NOR with
CONFIG_POSITION_INDEPENDENT=y. Unless fixing this issue, it is better
to revert this change.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-09-02 10:17:45 -04:00
Tom Rini
7cfbba36e9 Convert CONFIG_SYS_MALLOC_LEN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MALLOC_LEN

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-31 17:47:49 -04:00
Tom Rini
49c8ef0e45 Convert CONFIG_SYS_LOAD_ADDR to Kconfig
Now that we have consistent usage, migrate this symbol to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-31 17:46:37 -04:00
Tom Rini
df59b7d23b configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-26 21:10:37 -04:00
Masami Hiramatsu
10189cb700 configs: synquacer: Ignore OsIndications on DeveloperBox
Since we can not set OsIndications from Runtime Services
SetVariables at this moment, it is better to ignore the
OsIndications if there is any capsule file in the
correct place.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Masami Hiramatsu
9e2c1fefde configs: synquacer: Use RAW capsule image instead of FIT
Since the recent commit;

 commit b891ff18f8 ("efi_loader: Force a single FMP instance per hardware store")

forces a single FMP instances for a storage, we can not
enable both RAW and FIT capsule image support at once.
Since RAW capsule image support is simpler than FIT,
enable RAW capsule image instead of FIT by default.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Masami Hiramatsu
f4f11985bd configs: synquacer: Enable UEFI secure boot
Enable UEFI secure boot on synquacer. Note that unless user
setup their keys, the secure boot will not work.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Masami Hiramatsu
62c0136f36 configs: synquacer: Drop Ext2/4 support by default
Since the U-Boot for the SynQuacer DeveloperBox is designed for
compatible with EDK2 boot, we don't need to support Ext2/4 fs
support by default. Drop it.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Masami Hiramatsu
59bd18d4c4 configs: synquacer: Remove mtdparts settings and update DFU setting
Since MTD partitions are based on the devicetree name,
remove unneeded mtdparts settings and update DFU setting.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Masami Hiramatsu
f7e16bb0c5 configs: synquacer: Make U-Boot binary position independent
Make the U-Boot binary for SynQuacer position independent so
that the previous bootloader (SCP firmware or BL2) can load
the U-Boot anywhere.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-23 18:53:45 -04:00
Tom Rini
fd075f77ca configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 09:33:10 -04:00
Masami Hiramatsu
3a37386f18 configs: synquacer: Enable EFI capsule update support
Enable EFI capsule update support. With the EFI capsule update,
you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are
usually combined as a FIP binary, but if the binary is bigger
than 480KB, you have to modify FIP header, split the OP-TEE
and stores the OP-TEE binary in the different place. This
configuration supports both cases.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06 14:11:50 -04:00
Masami Hiramatsu
5cd4a355e0 board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.

For more information, see this page;
  https://www.96boards.org/product/developerbox/

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06 14:11:50 -04:00