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22605 commits

Author SHA1 Message Date
Kunihiko Hayashi
26dd38af85 clk: uniphier: Add missing USB SS-PHY clocks
The USB SS-PHY needs its own clock, however, some clocks don't have
clock gates. Define missing clock entries for the PHY as reference
clock.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
1c866de57b reset: uniphier: Add USB glue reset support
Add reset control support in USB glue logic. This needs to control
the external clocks and resets for the logic before accessing the
glue logic.

The USB dm tree when using dwc3-generic is the following:

   USB glue
     +-- controller       (need controller-reset)
     +-- controller-reset (need syscon-reset)
     +-- phy

The controller needs to deassert "controller-reset" in USB glue before
the controller registers are accessed. The glue needs to deassert
"syscon-reset" before the glue registers are accessed.

The glue itself doesn't have "syscon-reset", so the controller-reset
controls "syscon-reset" instead.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
211a066876 usb: dwc3-generic: Add the size of regs property to glue structure
Add the size of regs property to the glue structure to correctly
specify the register region to map.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
ef2313b8a2 usb: dwc3-generic: Export glue structures and functions
In order to allow external SoC-dependent glue drivers to use dwc3-generic
functions, push the glue structures and export the functions to a header
file.

The exported structures and functions are:

- struct dwc3_glue_data
- struct dwc3_glue_ops
- dwc3_glue_bind()
- dwc3_glue_probe()
- dwc3_glue_remove()

The SoC-dependent glue drivers can only define their own wrapper driver
and specify these functions. The drivers can also add their own compatible
strings and configure functions.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
7c71c684ce usb: dwc3-generic: Add clock initialization in child DT node
Same as the reset cotnrol, should add a clock initialization in child DT
node, if the glue node doesn't have any clocks.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Kunihiko Hayashi
f7b7c72133 usb: dwc3-generic: Allow different controller DT node pattern
The most of devicetree has the following USB node structure.
The controller node is placed as a child node of the glue node.
Current dwc3-generic driver works on this premise.

    glue {
        /* glue node */
	usb {
            /* controller node */
	};
    };

However, UniPhier original devicetree has the following USB node structure.
The controller node is separately placed from the glue node.

    usb {
        /* controller node */
    };
    glue {
        /* glue node */
    };

In dwc_glue_bind(), this patch provides .glue_get_ctrl_dev() callback to
get such a controller node and binds the driver related to the node.

If this callback isn't defined, dwc_glue_bind() looks for the controller
nodes from the child nodes, as before.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-02-22 19:40:11 +01:00
Marek Vasut
c6583354b7 usb: dwc3: Look up reference clock DT phandle in both controller DT nodes
There are currently four disparate placement possibilities of DWC3
reference clock phandle in SoC DTs:
- in top level glue node, with generic subnode without clock (ZynqMP)
- in top level generic node, with no subnode (i.MX8MQ)
- in generic subnode, with other clock in top level node (i.MX8MP)
- in both top level node and generic subnode (Rockchip)

Cover all the possibilities here by looking into both nodes, start
with the top level node as that seems to be used in majority of DTs
to reference the clock.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-02-22 19:40:11 +01:00
Simon Glass
e316fbabbf dm: treewide: Complete migration to new driver model schema
Update various build and test components to use the new schema.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-14 09:43:27 -07:00
Simon Glass
c74e03417b dm: Add support for handling old u-boot,dm- tags
Add a CONFIG option to deal with this automatically, printing a warning
when U-Boot starts up. This can be useful if the device tree comes from
another project.

We will maintain this through the 2023.07 release, providing 6 months
for people to notice.

Signed-off-by: Simon Glass <sjg@chromium.org>
Version 4:
Acked-by: Michal Simek <michal.simek@amd.com>
2023-02-14 09:42:14 -07:00
Pei Yue Ho
f536fda99f i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
Enable driver to fetch the optional parameter (fifo-depth) from device
tree. If the parameter is not found in the device tree, it will use
the default value declared in the driver.

Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:58:27 +01:00
Ryan Chen
4088f5fce8 i2c:aspeed:support ast2600 i2c new register mode driver
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:57:49 +01:00
Fabio Estevam
371be1e012 i2c: mxc_i2c: Use hex notation for the base address
Printing the I2C controller base address in decimal notation
is not helpful.

Change it to hex notation, which is the standard format found
in the Reference Manual and devicetree.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-02-13 09:57:30 +01:00
Tom Rini
9345f165eb Clock changes for 2023.04-rc1
This contains various fixes and small features. I've included a reset patch as
 well since it was in the same series as a clock patch.
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Merge tag 'clk-2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-clk

Clock changes for 2023.04-rc1

This contains various fixes and small features. I've included a reset patch as
well since it was in the same series as a clock patch.
2023-02-12 15:25:32 -05:00
Tom Rini
386e77cda8 Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
- A fix for a long standing bug that has been exposed by commit
  50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
  from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
2023-02-12 15:25:09 -05:00
Samuel Holland
5a675abfe7 reset: Allow reset_get_by_name() with NULL name
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
2023-02-12 13:44:20 -05:00
Samuel Holland
2050f824e1 clk: Allow clk_get_by_name() with NULL name
This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-02-12 13:44:20 -05:00
Dario Binacchi
4a18d23039 clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b]

According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):

     Clock Root         offset     Source Select (CCM_TARGET_ROOTn[MUX])
        ...              ...                    ...
 ENET_PHY_REF_CLK_ROOT  0xAA80            000 - 24M_REF_CLK
                                          001 - SYSTEM_PLL2_DIV20
                                          010 - SYSTEM_PLL2_DIV8
                                          011 - SYSTEM_PLL2_DIV5
                                          100 - SYSTEM_PLL2_DIV2
                                          101 - AUDIO_PLL1_CLK
                                          110 - VIDEO_PLL_CLK
                                          111 - AUDIO_PLL2_CLK
        ...              ...                    ...

while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
2023-02-12 12:39:46 -05:00
Dario Binacchi
e02bf587d3 clk: imx: rename video_pll1 to video_pll
[backport from linux commit bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]

Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.

No functional changes intended.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
2023-02-12 12:39:46 -05:00
Dario Binacchi
d0cc6a6ca1 clk: imx8mn: rename vpu_pll to m7_alt_pll
[backport from linux commit a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]

The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
2023-02-12 12:39:46 -05:00
Jim Liu
07f5399f04 clk: nuvoton: fix bug for calculate pll clock
Fix bug for npcm7xx bmc calculate pll clock.
PLLCON1 need to divide by 2.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
2023-02-12 12:39:46 -05:00
Simon Glass
4aa5053da5 timer: Tidy up use of notrace
Tracing is typically enabled by the time driver model starts up, so there
is no point in adding a 'notrace' to the timer-init function. However,
once the driver model timer is enabled, we do need to be able to access
the timer's private data when reading the timer, so add it to the core
function needed for that.

Update the function's documentation while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-11 12:22:34 -05:00
Tom Rini
ecff2bc4bd usb: gadget: Fix typo in obj line
When dropping the unused fotg210 gadget driver a leading 0 was
introduced to the next line, drop it.

Fixes: e9b4678bc7 ("usb: Drop unused fotg210 gadget")
Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-11 09:25:44 -05:00
Christophe Leroy
773ad4ebb1 spi, mpc8xx: Add support for chipselect via GPIO and fixups
This patch fixes the mpc8xx SPI driver:
- A stub callbacks for mode and speed,
- Use chip selects defined as GPIOs,
- Write proper value to disable relocation, other it fails on mpc885,
- Don't modify ports setup, ports can be different from one board to
another and are already set by board_early_init_r().

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-11 08:47:58 +01:00
Christophe Leroy
0223939498 driver, gpio: Add support for MPC 8xx CPU ports
Ports A, C and D are 16 bits ports.
Ports B and E are 32 bits ports.

The "compatible" is used to determine each port type.

This patch was originally written by Charles Frey who's
email address is not valid anymore as he left the company.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: FRANJOU Stephane <stephane.franjou@csgroup.eu>
2023-02-11 08:47:58 +01:00
Sergei Antonov
add396d667 net: ftmac100: add mii read and write callbacks
Register mii_bus with read and write callbacks to allow the 'mii'
command to work. Use a timeout of 10 ms to wait for the R/W
operations to complete.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
2023-02-10 13:41:07 -05:00
Sergei Antonov
9628c3e8b1 net: ftmac100: simplify priv->iobase casting
Replace 'phys_addr_t iobase' with 'struct ftmac100 *ftmac100' in
struct ftmac100_data. It allows to remove casting in a number of places.

Since priv->iobase is phys_addr_t, use phys_to_virt() to make
a pointer from it.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-10 13:41:07 -05:00
Sergei Antonov
e9a1d8bfc9 net: ftmac100: change driver name from nds32_mac to ftmac100
So it will be named similarly to the related ftgmac100 driver.
The old name 'nds32_mac' is not referred to anywhere in U-Boot.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-10 13:41:07 -05:00
Dzmitry Sankouski
e877996289 dm: input: add button_kbd driver
Bootmenu requires an input device with arrows and enter key.
A common smartphone luckily has power, volume up/down buttons,
which may be used for controlling bootmenu.
To use driver, add 'button-kbd' to stdin.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10 13:41:06 -05:00
Dzmitry Sankouski
ea6fdc1359 dm: button: add support for linux_code in button-gpio.c driver
Linux event code must be used in input devices, using buttons.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-10 12:50:01 -05:00
Dzmitry Sankouski
42a0c908dd gpio: qcom: add direction functions for pwrkey
GPIO button driver requires direction functions to probe
button gpio. Those functions are blank, since pwrkey is not
really gpio, and don't support direction settings.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
9bdec960b2 i2c: Add support for Qualcomm I2C driver
Add support for Qualcomm I2C QUP driver which is inspired from
corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c.

Currently this driver only support FIFO polling mode which is sufficient
to support devices like eeprom, rtc etc.

Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-02-10 12:50:00 -05:00
Sumit Garg
d382025dc5 net: dwc_eth_qos: Add Qcom ethernet driver glue layer
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be
configured according to following link speeds:
- SPEED_1000
- SPEED_100
- SPEED_10

So add a corresponding glue driver to configure RGMII macro.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10 12:50:00 -05:00
Sumit Garg
a962b7cff4 net: dwc_eth_qos: Allow platform to override tx/rx_fifo_sz
The GMAC controller on QCS404 SoC (support added by upcoming patch) fails
to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So
allow platforms to override FIFO size using corresponding DT node
properties.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10 12:50:00 -05:00
Sumit Garg
9d53f335f6 net: dwc_eth_qos: Make eqos_get_tick_clk_rate callback optional
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-02-10 12:50:00 -05:00
Simon Glass
42a13b21dc Correct SPL use of ATMEL_PIO4
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ATMEL_PIO4 defined in Kconfig

Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 08:22:52 -05:00
Simon Glass
ba490b251c Correct SPL use of PANEL
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_PANEL defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
68be8d95de Correct SPL uses of OF_BOARD
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_OF_BOARD defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
2023-02-10 07:41:41 -05:00
Simon Glass
c6228edf1f Correct SPL uses of FASTBOOT_FLASH_NAND
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH_NAND defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-02-10 07:41:41 -05:00
Simon Glass
7cb10e516b Correct SPL uses of FASTBOOT_FLASH_MMC
This converts 5 usages of this option to the non-SPL form, since there is
no SPL_FASTBOOT_FLASH_MMC defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2023-02-10 07:41:41 -05:00
Simon Glass
90210ceedc Correct SPL use of ARCH_VERSAL
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_ARCH_VERSAL defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
1b81aed125 Correct SPL uses of DISPLAY_AER_BRIEF
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_DISPLAY_AER_BRIEF defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
8581d9927d Correct SPL uses of ZYNQMP_FIRMWARE
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_ZYNQMP_FIRMWARE defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
2413fe67db Correct SPL uses of XEN_SERIAL
This converts 4 usages of this option to the non-SPL form, since there is
no SPL_XEN_SERIAL defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:41 -05:00
Simon Glass
b671359069 Correct SPL use of VIDEO_BPP32
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_VIDEO_BPP32 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
72129e088a Correct SPL use of VIDEO_BPP16
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_VIDEO_BPP16 defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
0ff8bb8724 Correct SPL uses of USB_MUSB_HOST
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_USB_MUSB_HOST defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
0b1671bc0f Correct SPL use of TPM_RNG
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_TPM_RNG defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
d179f865bf Correct SPL use of SUPPORT_EMMC_RPMB
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SUPPORT_EMMC_RPMB defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-10 07:41:40 -05:00
Simon Glass
4051c400c5 Correct SPL uses of SANDBOX_CLK_CCF
This converts 12 usages of this option to the non-SPL form, since there is
no SPL_SANDBOX_CLK_CCF defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00
Simon Glass
ef746bfd2c Correct SPL use of SANDBOX
This converts 1 usage of this option to the non-SPL form, since there is
no SPL_SANDBOX defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:40 -05:00