Commit graph

53244 commits

Author SHA1 Message Date
Marek Vasut
26cc40d8c4 mmc: dw_mmc: Add RCRC handling
This patch adds check for command response CRC failure. The driver
is currently ignoring CRC check failure on command resposes which
have CRC atteched to it, which can be potentially dangerous. Even
more grueling problem happens when the command response is followed
by data transfer though, as in that case, the dwmci_data_transfer()
function will spin until it reaches the 240s timeout.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-10 08:16:30 -05:00
Jun Nie
fb3148a230 common: build ymodem only on need
Build ymodem only on need to shrink spl image size.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
2018-11-09 13:45:42 -05:00
Lars Povlsen
6b0afcc850 common: Compile error with CONFIG_MULTI_DTB_FIT and not SPL
common/common_fit.c is including <spl.h>, but not actually using it. The
inclusion will cuase compile error on platforms using CONFIG_OF_SEPARATE
and not SPL.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-11-09 10:44:50 -05:00
Andy Shevchenko
cdef6bb43c dm: Fix typo - missed semicolon
The commit

  484fdf5ba0 ("dm: Add support for all targets which requires MANUAL_RELOC")

introduces subtle typo, i.e. missed semicolon.

Fixes: 484fdf5ba0 ("dm: Add support for all targets which requires MANUAL_RELOC")
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2018-11-09 10:44:50 -05:00
Simon Goldschmidt
30c0740e79 spl: fix debug prints for tiny printf
Tiny printf does not support %.*s and %lX. Since tiny printf should
be very common in SPL, replace these by %32s (for printing image
name) and %lx.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-09 10:44:50 -05:00
Patrick Delaunay
84ee59a5fd MAINTAINERS: Update stm32mp entry
Add mailing list for stm32mp architecture and board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-09 10:44:50 -05:00
Stefan Roese
6514bfc298 fit: Add missing CR in debug output in fit_find_config_node()
Testing has shown that a line-break is missing in one debug line in
fit_find_config_node().

Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-09 10:44:50 -05:00
Tom Rini
711720a0b3 Merge branch 'master' of git://git.denx.de/u-boot-ubi 2018-11-08 07:15:29 -05:00
Bin Meng
c5bbfaf05d imx8qxp_mek: Disable CONFIG_DISPLAY_CPUINFO
Due to revert of commit c0434407b5, this board does not build
any more. Disable CONFIG_DISPLAY_CPUINFO for v2018.11 release.

This commit should be reverted after v2018.11 release.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-07 12:13:45 -05:00
Bin Meng
5764ea2df4 Revert "board_f: Use static print_cpuinfo if CONFIG_CPU is active"
This reverts commit c0434407b5.

It turns out commit c0434407b5 broke some boards which have DM CPU
driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail
to boot when print_cpuinfo() is called during boot.

Fixes are already sent to ML and in u-boot-dm/next, however since
we are getting close to the v2018.11 release, it's safer we revert
the original commit.

This commit should be reverted after v2018.11 release.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-07 12:13:35 -05:00
Tom Rini
f63f65e489 Xilinx fixes for v2018.11-rc3
- Fix fit loading address for Zynq
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Merge tag 'xilinx-for-v2018.11-rc3' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.11-rc3

- Fix fit loading address for Zynq
2018-11-07 07:10:02 -05:00
Michal Simek
acb83bb3ec arm: zynq: Setup non zero SPL FIT load address
Default setup is 0 which is incorrect place because it points to OCM
which is allocated for SPL only in our case.
Use address in DDR.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-07 10:07:31 +01:00
Paul Davey
e4aa10ba57 fs: ubifs: Fix UBIFS decompression on 64 bit
Add local size_t variable to crypto_comp_decompress as intermediate
storage for destination length to avoid memory corruption and incorrect
results on 64 bit targets.

This is what linux does for the various lz compression implementations.

Signed-off-by: Paul Davey <paul.davey@alliedtelesis.co.nz>
Cc: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
2018-11-07 08:49:27 +01:00
Tom Rini
dd610e616c Fix coverity issues for i.MX8
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Merge tag 'u-boot-imx-20181106' of git://git.denx.de/u-boot-imx

Fix coverity issues for i.MX8
2018-11-06 11:12:00 -05:00
Tom Rini
acf52fb26f Merge git://git.denx.de/u-boot-marvell 2018-11-06 10:37:31 -05:00
Tom Rini
8f78e70012 Merge git://git.denx.de/u-boot-x86 2018-11-06 08:23:32 -05:00
Stefan Roese
ae4c38a538 arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA
The new board version has the 2nd FPGA connected via CS# 0 instead of
2 on SPI bus 1. Change this setup in the DT accordingly. Please note
that this change does still work on the old board version because the
CS signal is not used on this board.

Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-06 13:21:13 +01:00
Stefan Roese
6843db9922 arm: mvebu: armada-xp-theadorable.dts: Add "spi-flash" compatible property
Add the "spi-flash" compatible string so that the generic sf_probe
driver can probe the SPI flash on the theadorable Armada-XP board.

Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-06 13:21:13 +01:00
Stefan Roese
a8483505e8 arm: mvebu: Move PCI(e) MBUS window to end of RAM
With patch 49b23e035d (pci: mvebu: Increase size of PCIe default mapping)
the mapping size for each PCI(e) controller was increased from 32MiB to
128MiB. This leads to problems on boards with multiple PCIe slots / ports
which are unable to map all PCIe ports, e.g. the Armada-XP theadorable:

DRAM:  2 GiB (667 MHz, 64-bit, ECC not enabled)
SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB
Cannot add window '4:f8', conflicts with another window
PCIe unable to add mbus window for mem at f0000000+08000000
Model: Marvell Armada XP theadorable

This patch moves the base address for the PCI(e) memory spaces from
0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now).
This gives move room and flexibility for PCI(e) mappings.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: VlaoMao <vlaomao at gmail.com>
2018-11-06 13:21:13 +01:00
Peng Fan
0ea82ba2b0 MAINTAINERS: add NXP linux team maillist as i.MX reviewer
Add NXP linux team upstream maillist as reviewer

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-11-06 11:26:21 +01:00
Fabio Estevam
78c640fed6 ARM: dts: fsl-imx8qxp-mek: Move regulator outside "simple-bus"
Commit 3c28576bb0 ("arm: dts: imx8qxp: fix build warining")
fixed the dts warning by removing the unnecessary
#address-cells/#size-cells, but the recommendation for regulators is not
to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator
accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2018-11-06 11:25:55 +01:00
Fabio Estevam
664fa567ef mx8mq_evk: README: Delete file introduced by mistake
board/freescale/mx8mq_evk/README has been introduced by mistake
in commit d0dd73974c ("imx: add i.MX8QXP MEK board support")

Remove it for now as this should be introduced when mx8mq_evk
support is in place.

Reported-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-11-06 11:24:36 +01:00
Peng Fan
47f7a9def7 tools: imx8image: flatten container header only when creating container
If there is no CONTAINER entry, there is no need to flatten container
header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-11-06 11:24:10 +01:00
Peng Fan
a9f7f1c585 tools: imx8image: fix coverity CID 184233
Fix:
CID 184233:    (NEGATIVE_RETURNS)
Using variable "container" as an index to array "imx_header.fhdr".

Reported-by: Coverity
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-11-06 11:23:59 +01:00
Peng Fan
df439e938c tools: imx8image: fix coverity CID 184234
Fix:
CID 184234:    (TAINTED_SCALAR)
Using tainted variable "header.num_images - 1" as an index into an array "header.img".

Reported-by: Coverity
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-11-06 11:23:45 +01:00
Peng Fan
fc61cc2ca3 tools: imx8image: check lseek return value
Check lseek return value.

Fix Coverity CID: 184236 184235 184232

Reported-by: Coverity
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2018-11-06 11:23:27 +01:00
Andy Shevchenko
24109bba6a x86: acpi: Remove redundant Offset (0x00)
New ACPI assembler issues a warning:

board/intel/edison/dsdt.asl.tmp     13:     Offset (0x00),
Remark   2158 -                                       ^ Unnecessary/redundant use of Offset operator

Indeed, in the OperationRegion the offset is 0x00 by default.

Thus, drop unneeded Offset() use as suggested by ACPI assembler.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-06 13:35:06 +08:00
Tom Rini
5ef76e59c1 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-11-04 08:12:21 -05:00
Tom Rini
5d6fefa805 Merge tag 'mips-fixes-for-v2018.11' of git://git.denx.de/u-boot-mips
- replace the dynamic size of the relocation table
  with a fixed but configurable size
- fixes non-working CONFIG_OF_SEPARATE=y due to invalid _end symbol
2018-11-03 08:21:05 -04:00
Daniel Schwierzeck
9630146411 MIPS: make size of relocation table fixed but configurable
Currently the size of the relocation table will be shrunk
to the actual size needed. Although this gives a maximal
space saving, it messes up the _end symbol. This breaks
features like appended DTBs because the _end symbol doesn't
point to the real end of the U-Boot binary.

Remove the size shrinking and make the size of the relocation
table fixed but configurable. This follows the Linux approach
and the user can adjust the size to his needs.

Also rename the relocation table section from .rel to .data.reloc
to follow the Linux approach and to avoid ambiguities with the
.rel.* sections added by the linker.

Reported-by: Lars Povlsen <lars.povlsen@microsemi.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-02 22:39:07 +01:00
Marek Vasut
a376dde1de mmc: tmio: sdhi: Merge DTCNTL access into single register write
It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:07:04 +01:00
Marek Vasut
2fc10754d1 mmc: tmio: sdhi: Implement waiting for DAT0 line state
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.

This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:45 +01:00
Marek Vasut
dc1488f1d2 mmc: tmio: sdhi: Clear HS400 settings when resetting SCC
Make sure to clear HS400 configuration when resetting the SCC block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:45 +01:00
Marek Vasut
52e1796883 mmc: tmio: sdhi: Touch SCC only when UHS capable
Add check to avoid touching the SCC tuning registers in case the IP
doesn't support them or if the support isn't in place yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:44 +01:00
Marek Vasut
c83da2ebc0 mmc: tmio: Preinitialize regulator to 3.3V
Preinitialize the SD card signals regulator to 3.3V, which is the
default post-reset setting, to be sure the regulator is set to a
valid value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
8171f99e7d mmc: tmio: Configure clock before any other IOS
Configure the clock settings before reconfiguring any other IO settings.
This is required when the clock must be stopped before changing eg. the
pin configuration or any of the other properties of the bus. Running the
clock configuration first allows the MMC core to do just that.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
33633ebb1c mmc: tmio: Silence transfer errors when tuning
In case the controller performs card tuning, that is, sends MMC
command 19 or 21, silence possible CRC error warning prints. The
warnings are bound to happen, since the tuning will fail for some
settings while searching for the optimal configuration of the bus
and that is perfectly OK.

This patch passes around the MMC command structure and adds check
into tmio_sd_check_error() to avoid printing CRC error warning
when the tuning happens.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
b22c8d0de4 mmc: tmio: Improve error handling
Properly handle return values and abort operations when they are
non-zero. This is a minor improvement, which fixes two remaining
unchecked return values.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
645a575aeb mmc: tmio: Simplify pinmux handling
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400
modes all use 1.8V signaling, while all the legacy modes use 3.3V
signaling. While there are extra modes which use 1.2V signaling,
the existing hardware does not support those.

Simplify the pinmux such that 3.3V signaling implies legacy mode
pinmux and the rest implies UHS mode pinmux. This prevents the
massive case statement from growing further. Moreover, it fixes
an edge case where during SD 1.8V switch, the bus mode is still
set to default while the signaling is already set to 1.8V, which
results in an attempt to communicate with a 1.8V card using pins
in 3.3V mode and thus communication failure.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
e5cb6bd9a2 ARM: rmobile: Generate fitting mem_map on Gen3
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.

This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes: c1ec347638 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3")
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Marek Vasut
5dbdd3a600 pinctrl: renesas: Add POCCTRL handling to r8a77990
Add definition of the POCCTRL register and bits therein to R8A77990 E3
pincontrol driver. This allows the pincontrol driver to configure SDHI
pin voltage according to power-source DT property.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Marek Vasut
0ff9e4800f pinctrl: renesas: Fix DRV register offset
Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Tom Rini
99431c1c21 Merge tag 'arc-for-2018.11' of git://git.denx.de/u-boot-arc
Just 2 non-functinal changes:

 1. Rename of EMDK to EMSDP so it matches real marketing name
 2. Add essential README for IoTDK
2018-11-02 09:39:18 -04:00
Alexey Brodkin
a6b8c29fb8 iot_dk: Add README
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01 23:04:05 +03:00
Alexey Brodkin
adc9b09a23 emdk->emsdp: Rename board
Real marketing name of the board was recently updated so
to accommodate that change renaming the board and all
related to it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01 23:04:05 +03:00
Sam Protsenko
de8566a160 arm: ti: boot: Don't read environment partition
This part should've been remove in commit 88d60db011 ("arm: ti: boot:
Remove environment partition"), but I missed it somehow. Remove reading
dtb file from environment partition on eMMC, as we don't have it
anymore.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2018-11-01 10:02:43 -04:00
Jens Wiklander
c091dc7dad test: tee: fix resource leak in dm_test_tee()
Fixes possible resource leak in dm_test_tee() reported by Coverity.

Reported-by: Coverity (CID: 184175)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-11-01 10:02:43 -04:00
Patrick Delaunay
be6eb23931 cmd: remove CONFIG_SOURCE support in Makefile
This line is no more needed and can be removed.

Only CONFIG_CMD_SOURCE is defined in Kconfig and
used in defconfig files.

CONFIG_SOURCE if not defined in source code and
"config SOURCE" is not present in any Kconfig.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-01 10:02:43 -04:00
Lokesh Vutla
26da01f700 power: spl: add SPL_DM_REGULATOR_GPIO in Kconfig
The Makefile already tests for SPL_DM_REGULATOR_GPIO, but Kconfig
does not provide it. This adds SPL_DM_REGULATOR_GPIO to Kconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-01 10:02:43 -04:00
Keerthy
1a25d9071b cmd: remoteproc: Fix the base of strtoul for ID conversion from 3 to 10
Currently the base is 3 fix it 10 so that IDs follow decimal system.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvulta@ti.com>
2018-11-01 10:02:43 -04:00