Commit graph

6 commits

Author SHA1 Message Date
Andrey Skvortsov
587c3f8ebe imx_watchdog: always set minimal timeout in reset_cpu
The problem is that timeout bits in WCR register were leaved unchanged.
So previously set timeout value was applied and therefore 'reset'
command takes any value up to two minutes, depending on previous
watchdog settings, instead of minimal 0.5 seconds.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
2016-01-07 17:54:53 +01:00
Fabio Estevam
f532727d16 imx_watchdog: Add a header file for watchdog registers
Create fsl_wdog.h to store the watchdog registers and bit fields.

This can be useful when accesses to the watchdog block are made from other
parts, such as arch/arm/ cpu code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-12 12:56:26 -04:00
Peng Fan
623d96e89a imx: wdog: correct wcr register settings
We should not simple use "writew(WCR_WDE, &wdog->wcr)" to set
wcr, since this will override bits set before reset_cpu.

Use clrsetbits_le16 instead of writew to fix this issue.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Sebastian Siewior <bigeasy@linutronix.de>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:39:35 +02:00
Sebastian Siewior
5cab874052 watchdog/imx_watchdog: do not set WCR_WDW
with WCR_WDW set, the watchdog won't trigger if we bootet linux and idle
around while the watchdog is not triggered. It seems the timer makes
progress very slowly if at all. I managed to remain 20minutes alive
while the timeout was set to 60secs. It reboots within 60secs if I start
a busyloop in userland (something like "while (1) { }").

While I don't see a reason why the WDT should not be running while the
CPU is in idle, I'm dropping this bit.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-03-25 16:52:16 +01:00
Anatolij Gustschin
723ec69a6b imx_watchdog: do not soft-reset while watchdog init
Currently the driver clears WCR_SRS bit when enabling
the watchdog and this causes a software reset. Do not
clear WCR_SRS.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-10-31 17:54:03 +01:00
Troy Kisky
abbab70363 mx31/mx35/mx51/mx53/mx6: add watchdog
Use a common watchdog driver for all these cpus.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-13 11:39:57 +01:00