Commit graph

115 commits

Author SHA1 Message Date
Sean Anderson
2667dacb42 usb: dwc3: Don't include asm-generic/io.h
This can conflict with asm/io.h on some archs, and it isn't needed to build
dwc3-generic.c

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:59 -04:00
Sean Anderson
44003f88a9 usb: dwc3: ti: Fix not calling dev_err with a device
This driver does not use DM, so use log_xxx instead.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:58 -04:00
Sean Anderson
df5eabcbf7 usb: dwc3: Fix not calling dev_xxx with a device
This logs with the device from struct dwc3. Some files also need to include
dm.h so fields in udevice can be accessed.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:54 -04:00
Robert Marko
74a703a8ad usb: dwc3: Add Qualcomm DWC3 compatible string
Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0
ports.
Qualcomm has some custom config registers on top of the generic ones,
but for host mode these are not needed.

So lets add the neccessary compatible string.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Masahiro Yamada
2548493ab4 treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25 14:46:57 -06:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Masahiro Yamada
60e7fa8b3b treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Frank Wang
5d422ab26d usb: dwc3: add make compatible for rockchip platform
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-30 07:38:50 +08:00
Frank Wang
646979425a usb: dwc3: amend UTMI/UTMIW phy interface setup
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:13:19 +08:00
Jagan Teki
fafaa02290 usb: dwc3: Enable AutoRetry feature in the controller
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).

Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.

Doing so will give controller a chance to recover from transient error
conditions.

Reference from below Linux commit,

commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
in the controller")

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:13:19 +08:00
Jagan Teki
dc18413adb usb: dwc3: Add disable u2mac linestate check quirk
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.

When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).

On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.

Reference from below Linux commit,

commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
check quirk")

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:13:19 +08:00
Frank Wang
b34f8b5de0 usb: dwc3: add dis_u2_freeclk_exists_quirk
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29 18:13:19 +08:00
Frank Wang
7bb6270839 usb: dwc3: add dis_enblslpm_quirk
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29 18:13:19 +08:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
eb41d8a1be common: Drop linux/bug.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Siva Durga Prasad Paladugu
648856ac19 usb: dwc3: Add versal compatibility string to dwc3 glue ids
Xilinx Versal platform uses dwc3 and hence its compatible string
needs to be added to dwc3 glue ids.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-05-12 09:27:14 +02:00
Jagan Teki
73ca0140e1 usb: dwc3: add dis_del_phy_power_chg_quirk
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Reference from below Linux commit,

commit <00fe081dc3a3> ("usb: dwc3: add dis_del_phy_power_chg_quirk")

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-12 09:27:14 +02:00
Chunfeng Yun
6dfb8a8052 usb: dwc3: use the phy bulk API to get phys
Get a group of phys by the phy bulk API

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02 12:32:28 +02:00
Neil Armstrong
3dc4f83970 usb: dwc3-meson-g12a: add power-on/off of the PHYs
Power on/off the PHYs to enable power to the USB ports, fixing USB support
on Khadas VIM3/VIM3L boards.

The G12A USB complex has at least 2 USB2 PHYs, but one is muxed between the
DWC2 and DWC3 controller and the other one directly connected to the DWC3
controller. The USB3+PCIe combo PHY is muxed between the DWC3 controller
and a DW-PCIE controller.
All PHYs are optional, but it's type (usb2/usb3) and position are important
to determine it's capabilities, thus they are stored in a fixed size
array and the phy-name determines it's position, it's position determining
it's type and functionnalities.
This is why we need to loop over the array to power on all the DT provided
PHYs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-04-28 10:23:10 +02:00
Kever Yang
ac28e59a57 usb: Migrate to support live DT for some driver
Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT.
This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use
ofnode as parameter instead of fdt offset. And all the drivers who use
these APIs update to use live dt APIs at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-30 03:48:53 +02:00
Masahiro Yamada
9d86b89c59 dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.

Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.

If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.

Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Masahiro Yamada
950c596867 dma-mapping: fix the prototype of dma_unmap_single()
dma_unmap_single() takes the dma address, not virtual address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
61b29b8268 dm: core: Require users of devres to include the header
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Vignesh Raghavendra
cab4e275dd dwc3-generic: Add support for AM654 USB controller
AM654 has DWC3 USB controller that is very similar to other TI SoCs. Add
a new compatible to enable the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:29 +05:30
Jagan Teki
5c207282f5 usb: dwc3: Fix UTMI/UTMIW phy interface initialization
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.

The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.

So, handle the phy masking bits accordingly on respective interface
type cases.

Fixes: 6b7ebff001 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-21 20:35:16 +01:00
Simon Glass
1eb69ae498 common: Move ARM cache operations out of common.h
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:58 -05:00
Jagan Teki
6b7ebff001 usb: dwc3: Add phy interface for dwc3_uboot
U-Boot has two different variants of dwc3 initializations,
- with dm variant gadget, so the respective dm driver would
  call the dwc3_init in core.
- with non-dm variant gadget, so the usage board file would
  call dwc3_uboot_init in core.

The driver probe would handle all respective gadget properties
including phy interface via phy_type property and then trigger
dwc3_init for dm-variant gadgets.

So, to support the phy interface for non-dm variant gadgets,
the better option is dwc3_uboot_init since there is no
dedicated controller for non-dm variant gadgets.

This patch support for adding phy interface like 8/16-bit UTMI+
code for dwc3_uboot.

This change used Linux phy.h enum list, to make proper code
compatibility.

Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Marek Szyprowski
fd15b58c1a dwc3: flush cache only if there is a buffer attached to a request
Calling cache flush on invalid buffer, even with zero length might cause
an exception on certain platforms.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2019-10-31 12:12:31 +01:00
Vignesh Raghavendra
d624434f5e dwc3-generic: Don't fail probe if clk/reset entries are absent
Some boards don't populate clk/reset entries as these are are optional
as per binding documentation. Therefore, don't fail driver probe if
clk/reset entries are absent in DT.

This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx

Fixes: e8e683d33b ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-10-31 12:11:24 +01:00
Jean-Jacques Hiblot
3e6ab7327f usb: dwc3: Kconfig: get rid of obsolete mode selection
The mode selection for the DWC3 is kind of obsolete. The driver does not
have to be host only or gadget only. This choice is confusing.
All the remaining callers of dwc3_uboot_init() explicitly set dr_mode
before calling the function, so none rely on a default behavior.

Remove the choice menu and keep only the USB_DWC3_GADGET option. Enable it
by default if USB_GADGET and USB_DWC3 are enabled.
It must be disabled for the evb-rk3328 as it uses DWC2 for the gadget and
DWC3 for the host.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
ba6c5f7a28 usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1a63e5e5fb usb: dwc3-generic: if no max speed is specified in DT, assume super speed
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
b575e90916 usb: dwc3-generic: add a new host driver that uses the dwc3 core
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".

In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1af590df16 usb: dwc3-generic: factorize code
Factor code for re-usability.
This is another step toward adding host support.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
3a38a0adb9 usb: dwc3-generic: use platdata
Separate platform data from the private data.
This is one step toward adding host support.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
33a99b4365 usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
bbe3d4a6c1 usb: dwc3: switch to peripheral mode when exiting
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:16 +02:00
T Karthik Reddy
1a031d236a drivers: usb: dwc3: setup phy before dwc3 core soft reset
Phy setup should be done before dwc3 soft core reset as it is done
in linux & this fixes unreliable detection of usb cable on host side.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:41:27 +02:00
Jean-Jacques Hiblot
3b83829ed6 usb: dwc3: Use UCLASS_NOP instead of UCLASS_MISC for the DWC3 generic glue
dwc3-generic has been broken since MISC uclass has been modified to scan DT
sub-nodes after bind.
Fixing it by a using the no-op uclass.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-05 14:19:41 +02:00
Jean-Jacques Hiblot
e445d46651 usb: dwc3-generic: remove dm_scan_fdt_dev() from the remove() callback
There is simply no reason to do that here.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-05 14:19:40 +02:00
Neil Armstrong
adb049abf7 usb: dwc3: Add Meson G12A USB Glue
Adds support for Amlogic G12A USB Control Glue HW.

The Amlogic G12A SoC Family embeds 2 USB Controllers :
- a DWC3 IP configured as Host for USB2 and USB3
- a DWC2 IP configured as Peripheral USB2 Only

A glue connects these both controllers to 2 USB2 PHYs, and optionnally
to an USB3+PCIE Combo PHY shared with the PCIE controller.

The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including
routing of the OTG PHY between the DWC3 and DWC2 controllers, and
setups the on-chip OTG mode selection for this PHY.

This driver sets the OTG capable port as Host mode by default,
the switch to Device mode is to be done in a separate patch.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-05-09 10:38:32 +02:00
Jean-Jacques Hiblot
1ce5f1f933 dwc3-generic: Add support for the am437x
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:09 +01:00
Jean-Jacques Hiblot
1c03ade328 usb: dwc3-generic: make it compatible with "ti, keystone-dwc3"
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-14 17:59:09 +01:00
Lukasz Majewski
916fa09799 usb: composite: Move bitmap related operations to ./include/linux/bitmap.h
The BITMAP related operations can now be moved to ./include/linux/bitmap.h
file to mimic the Linux kernel directory tree.

This change also allows to remove the lin_gadget_compat.h header file
(which is a legacy code only for composite U-boot layer).
It was also possible to remove #includes from several USB gadget drivers.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2018-12-14 17:59:08 +01:00
Jean-Jacques Hiblot
d66e54ac80 dwc3-generic: Add support for the TI DWC3 glue
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-12-07 16:31:46 +01:00
Jean-Jacques Hiblot
4d3825c191 usb: dwc3: Fix a compilation error with the edison defconfig
The error is:
In file included from include/part.h:10:0,
                 from include/usb.h:18,
                 from include/linux/usb/gadget.h:22,
                 from drivers/usb/dwc3/ep0.c:20:
include/ide.h:62:14: error: unknown type name ‘uchar’
 void ide_led(uchar led, uchar status);

Fixing it by including common.h that defines the uchar type.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-12-07 16:31:45 +01:00
Jean-Jacques Hiblot
93991cf196 dwc3-generic: Add select_dr_mode operation
The select_dr_mode operation is executed when the glue driver is probed.
The role of this optional function is to configure the operating mode
of the controller at the glue level.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-12-07 16:31:45 +01:00