Commit graph

25050 commits

Author SHA1 Message Date
Simon Glass
1ca7e2062b dm: Provide a function to scan child FDT nodes
At present only root nodes in the device tree are scanned for devices.
But some devices can have children. For example a SPI bus may have
several children for each of its chip selects.

Add a function which scans subnodes and binds devices for each one. This
can be used for the root node scan also, so change it.

A device can call this function in its bind() or probe() methods to bind
its children.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:36 +01:00
Simon Glass
0040b94429 dm: Tidy up some header file comments
Fix up the style of a few comments and add/clarify a few others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
3234aa4bab fdt: Add a function to get the node offset of an alias
This simple function returns the node offset of a named alias.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
c910e2e2da dm: Avoid accessing uclasses before they are ready
Don't allow access to uclasses before they have been initialised.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
f4cdead24a dm: Allow a device to be found by its FDT offset
Each device that was bound from a device tree has an node that caused it to
be bound. Add functions that find and return a device based on a device tree
offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
b7d665705e dm: Display the sequence number for each device
Add this information to 'dm tree' and 'dm uclass' commands.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
5a66a8ff86 dm: Introduce device sequence numbering
In U-Boot it is pretty common to number devices from 0 and access them
on the command line using this numbering. While it may come to pass that
we will move away from this numbering, the possibility seems remote at
present.

Given that devices within a uclass will have an implied numbering, it
makes sense to build this into driver model as a core feature. The cost
is fairly small in terms of code and data space.

With each uclass having numbered devices we can ask for SPI port 0 or
serial port 1 and receive a single device.

Devices typically request a sequence number using aliases in the device
tree. These are resolved when the device is probed, to deal with conflicts.
Sequence numbers need not be sequential and holes are permitted.

At present there is no support for sequence numbers using static platform
data. It could easily be added to 'struct driver_info' if needed, but it
seems better to add features as we find a use for them, and the use of -1
to mean 'no sequence' makes the default value somewhat painful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
4e8bc21170 dm: Avoid activating devices in 'dm uclass' command
This command currently activates devices as it lists them. This is not
desirable since it changes the system state. Fix it and avoid printing
a newline if there are no devices in a uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
fffa24d7c5 dm: Move device display into its own function
The device display for 'dm tree' and 'dm uclass' is mostly the same, so
move it into a common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
5c33c9fdbb fdt: Add a function to get the alias sequence of a node
Aliases are used to provide U-Boot's numbering of devices, such as:

aliases {
	spi0 = "/spi@12330000";
}

spi@12330000 {
	...
}

This tells us that the SPI controller at 12330000 is considered to be the
first SPI controller (SPI 0). So we have a numbering for the SPI node.

Add a function that returns the numbering for a node assume that it exists
in the list of aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
9ca296a1b0 dm: Move uclass error checking/probing into a function
Several functions will use this same pattern, so bring it into a function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
093f79ab88 Add a flag indicating when the serial console is ready
For sandbox we have a fallback console which is used very early in
U-Boot, before serial drivers are available. Rather than try to guess
when to switch to the real console, add a flag so we can be sure. This
makes sure that sandbox can always output a panic() message, for example,
and avoids silent failure (which is very annoying in sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
7793ac96c6 console: Remove vprintf() optimisation for sandbox
If the console is not present, we try to reduce overhead by stopping any
output in vprintf(), before it gets to putc(). This is of dubious merit
in general, but in the case of sandbox it is incorrect since we have a
fallback console which reports errors very early in U-Boot. If this is
defeated U-Boot can hang or exit with no indication of what is wrong.

Remove the optimisation for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
d97143a67c stdio: Provide functions to add/remove devices using stdio_dev
The current functions for adding and removing devices require a device name.
This is not convenient for driver model, which wants to store a pointer to
the relevant device. Add new functions which provide this feature and adjust
the old ones to call these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
ab7cd62790 dm: Support driver model prior to relocation
Initialise devices marked 'pre-reloc' and make them available prior to
relocation. Note that this requires pre-reloc malloc() to be available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
00606d7e39 dm: Allow drivers to be marked 'before relocation'
Driver model currently only operates after relocation is complete. In this
state U-Boot typically has a small amount of memory available. In adding
support for driver model prior to relocation we must try to use as little
memory as possible.

In addition, on some machines the memory has not be inited and/or the CPU
is not running at full speed or the data cache is off. These can reduce
execution performance, so the less initialisation that is done before
relocation the better.

An immediately-obvious improvement is to only initialise drivers which are
actually going to be used before relocation. On many boards the only such
driver is a serial UART, so this provides a very large potential benefit.

Allow drivers to mark themselves as 'pre-reloc' which means that they will
be initialised prior to relocation. This can be done either with a driver
flag or with a 'dm,pre-reloc' device tree property.

To support this, the various dm scanning function now take a 'pre_reloc_only'
parameter which indicates that only drivers marked pre-reloc should be
bound.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
6133683320 sandbox: Remove all drivers before exit
Drivers are supposed to be able to close down cleanly. To set a good example,
make sandbox shut down its driver model drivers and remove them before exit.

It may be desirable to do the same more generally once driver model is more
widely-used. This could be done during bootm, before U-Boot jumps to the OS.
It seems far too early to make this change.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
9adbd7a116 dm: Provide a way to shut down driver model
Add a new method which removes and unbinds all drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:24 +01:00
Simon Glass
7497812d47 dm: Make sure that the root device is probed
The root device should be probed just like any other device. The effect of
this is to mark the device as activated, so that it can be removed (along
with its children) if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:24 +01:00
Simon Glass
709ea543b9 stdio: Pass device pointer to stdio methods
At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.

For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.

Instead, add a stdio_dev pointer to each of the stdio member functions.

Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.

Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.

22: stdio: Pass device pointer to stdio methods
       arm: (for 2/2 boards)  all +244.0  bss -4.0  text +248.0
   powerpc: (for 1/1 boards)  all +428.0  text +428.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Simon Glass
91d0be1dd8 stdio: Remove redundant code around stdio_register() calls
There is no point in setting a structure's memory to NULL when it has
already been zeroed with memset().

Also, there is no need to create a stub function for stdio to call - if the
function is NULL it will not be called.

This is a clean-up, with no change in functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Simon Glass
eb9ef5fee7 dm: Use an explicit expect value in core tests
Rather than reusing the 'reg' property, use an explicit property for the
expected ping value used in testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:23 +01:00
Simon Glass
5b9765c7d6 dm: gpio: Don't use the driver model uclass for SPL
Driver model does not support SPL yet, so we should not use the GPIO
uclass for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:23 +01:00
Simon Glass
6d7601e744 sandbox: Always enable malloc debug
Tun on DEBUG in malloc(). This adds code space and slows things down but
for sandbox this is acceptable. We gain the ability to check for memory
leaks in tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:06:17 +01:00
Simon Glass
b53e94b132 sandbox: config: Enable pre-relocation malloc()
Enable this for sandbox so that we will be able to use driver model before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:06:17 +01:00
Simon Glass
29afe9e6ed sandbox: Support pre-relocation malloc()
Set up and zero global data before board_init_f() is called so that we can
remove the need for CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:06:13 +01:00
Simon Glass
d59476b644 Add a simple malloc() implementation for pre-relocation
If we are to have driver model before relocation we need to support some
way of calling memory allocation routines.

The standard malloc() is pretty complicated:

1. It uses some BSS memory for its state, and BSS is not available before
relocation

2. It supports algorithms for reducing memory fragmentation and improving
performace of free(). Before relocation we could happily just not support
free().

3. It includes about 4KB of code (Thumb 2) and 1KB of data. However since
this has been loaded anyway this is not really a problem.

The simplest way to support pre-relocation malloc() is to reserve an area
of memory and allocate it in increasing blocks as needed. This
implementation does this.

To enable it, you need to define the size of the malloc() pool as described
in the README. It will be located above the pre-relocation stack on
supported architectures.

Note that this implementation is only useful on machines which have some
memory available before dram_init() is called - this includes those that
do no DRAM init (like tegra) and those that do it in SPL (quite a few
boards). Enabling driver model preior to relocation for the rest of the
boards is left for a later exercise.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:05:40 +01:00
Simon Glass
4d94dfa059 sandbox: Set up global data before board_init_f()
At present sandbox defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f().

If we set up and zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change to simplify the init process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:05:39 +01:00
Simon Glass
d93041a4ca Remove form-feeds from dlmalloc.c
These don't really serve any purpose in the modern age. On the other hand
they show up as annoying control characters in my editor, which then happily
removes them.

I believe we can drop these characters from the file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:02:58 +01:00
Shengzhou Liu
b0d97cd2ed powerpc/t1040: update i2c for t1040qds and t104xrdb
- Fix base address of I2C2 as 0x118100 instead of 0x119000.
- Add definitions for I2C3 & I2C4.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Tang Yuantian
7cb7272365 mpc85xx/t104x: Enable L2 and CPC cache when resume
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaveta Leekha
a1399a9187 powerpc/chassis2: Configure and enable L2 cache for PPC clusters only
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaohui Xie
e55782eccc powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
3d75ec95f5 driver/ddr: Fix DDR register timing_cfg_8
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaohui Xie
de51916310 powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
9d0456822c powerpc/mpc85xx: Check return value of find_tlb_idx
find_tlb_idx() is called in board_early_init_r() on multiple boards.
The return value is not checked before being used to disable a TLB.
In normal case the return value wouldn't be -1. In case of a mis-
configuration during porting to a new board, checking the return value
may be helpful to reveal some user errors.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
vijay rai
6666017f44 powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
591dd19230 driver/nand: Add support of 16K SRAM for IFC 2.0
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

Update the page offset calculation logic to support the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zang Roy-R61911
32514d259b fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint
Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
04818bbdc3 driver/nand: Update SRAM initialize logic for IFC.
IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.

update SRAM initialize logic to reflect the same.

Also print error message in case of Page read error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
3bab3d8324 driver/nand:Define MAX_BANKS same as SoC defined for IFC
The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Lijun Pan
d0bc51407c powerpc/mpc85xx: Remove P1023 RDS support
Since P1023RDS is no longer supported/manufactured by Freescale,
we clean up P1023RDS related code.
Since P1023RDB is still supported by Freescale,
we keep P1023RDB releated code.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Sandeep Singh
d43a386a91 powerpc/mpc85xx: Removed support for G4060
G4060 has no PA cores, hence removing its support.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zhao Qiang
38d67a4e55 qe: move immap_qe.h from arch directory into common directory
ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Shengzhou Liu
09c2046ff6 board/t2080qds: enable sst and eon spi flash for nor boot
Remove unnecessary condition CONFIG_RAMBOOT_PBL to
have SST and EON SPI flash work in case of NOR boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Rotariu Marian-Cristian
1155d8d853 net/fm: call fm_port_to_index() with proper checks
Some of the fm_port_to_index() callers did not check for -1 return value and
used -1 as an array index.

Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:53 -07:00
Shengzhou Liu
605714f669 powerpc/85xx: add fdt_fixup_dma3
On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is
chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:53 -07:00
Masahiro Yamada
fbe79a17fd m68k: define __kernel_size_t as unsinged int again
Commit ddc94378d changed the definition of __kernel_size_t
from unsigned int to unsigned long.

It is true that it fixed warnings on some crosstools
but it increased warnings on the others.

The problem is that we cannot see consistency in terms of
the typedef of __kernel_size_t on M68K architecture.

However, I'd like to suggest to have __kernel_size_t to be
unsigned int again.

Rationale:

[1] Linux Kernel defines __kernel_size_t on M68K as unsigned int.
    Let's stick to the Linux's way.

[2] We want to build boards with popular pre-built toolchains,
    not the one locally-built by indivisuals.
    I think m68-linux-gcc which can be downloaded from www.kernel.org
    is the candidate for our _recommended_ toolchains.

With this patch, all the m68k boards can be built without any warnings.

Give it a try with the following crosstools:

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/
x86_64-gcc-4.6.3-nolibc_m68k-linux.tar.xz

or

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_m68k-linux.tar.xz

(The latter is newer.)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-07-22 09:46:50 -04:00
Masahiro Yamada
61f06b143e m68k: fix an undefined behavior warning of M5253DEMO board
The latest GCC is so clever that it reports more warnings
than old ones did:

 ------------------------------>8------------------------------

  board/freescale/m5253demo/flash.c: In function 'flash_get_offsets':
  board/freescale/m5253demo/flash.c:65:23: warning: iteration 2047u
  invokes undefined behavior [-Waggressive-loop-optimizations]
      info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
                         ^
  board/freescale/m5253demo/flash.c:64:3: note: containing loop
     for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
     ^

 ------------------------------8<------------------------------

The cause of the warning is like this:

The for statement iterates 2048 times in flash_get_offsets() func.
(Notice CONFIG_SYS_SST_SECT is defined as 2048)

The last iteration does
  info->start[2048] = info->start[2047] + CONFIG_SYS_SST_SECTSZ;
causing an undefined behavior.

(Please note the array size of info->start is 2048.
CONFIG_SYS_MAX_FLASH_SECT is defined as 2048 for this board.)

This commit fixes that so as not to overrun the info->start array.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-07-22 09:46:48 -04:00