Commit graph

48288 commits

Author SHA1 Message Date
Lukasz Majewski
53e8ca2253 MAINTAINERS: DFU: Change e-mail address for DFU maintainer
Despite I leave Samsung by the end of the year, I'm going to maintain DFU
in u-boot.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2016-12-12 13:03:15 -05:00
Lukasz Majewski
dea6068817 MAINTAINERS: ONENAND: MTD: Mark Samsung's OneNAND as orphaned
Since I leave Samsung by the end of the year, I will not have access to
OneNAND devices anymore.

Hence the custodian position has been marked as "Orphaned".

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2016-12-12 10:54:37 -05:00
Tom Rini
b591730c35 Merge git://www.denx.de/git/u-boot-marvell 2016-12-12 07:19:28 -05:00
Tom Rini
fe9822556e Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-12-12 07:18:53 -05:00
Konstantin Porotchkin
a20b7a2a53 arm64: mvebu: Enable hush parser in A8K default configuration
Enable hush parser in Armada-7040 and Armada-8040 DB default
configurations.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:05:45 +01:00
Konstantin Porotchkin
1d136726f7 arm64: mvebu: Enable PCIe support in Armada-7040 configuration
Enable PCIe bus support in Armada-7040 DB default configuration

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:05:36 +01:00
Konstantin Porotchkin
b58385df3a arm64: mvebu: Add L3 cache flush functionality to A8K family
Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:05:28 +01:00
Konstantin Porotchkin
81647eaff3 arm64: mvebu: Enable pin control support in A8K default config
Enable mvebu pin control support in the default configuration
files for Armada-7040 and Armada-8040 development boards

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Konstantin Porotchkin
27bd4b159a arm64: mvebu: Enable BUBT command support in A8K default config
Enable mvebu "bubt" command support in the default configuration
file for Armada-7040 and Armada-8040 development boards

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Konstantin Porotchkin
f99386c5b1 arm64: mvebu: Add pin control nodes to A8K family DTS files
Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Konstantin Porotchkin
656e6cc86b arm64: mvebu: pinctrl: Add pin control driver for A8K family
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Konstantin Porotchkin
fa61ef6b49 arm64: mvebu: Add bubt command for flash image burn
Add support for mvebu bubt command for flash image
load, check and burn on boot device.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Konstantin Porotchkin
5b613d386a arm64: mvebu: Modify the A8K SPI and I2C config in DTS
Align the Armada-8040-db and Armada-7040-db SPI and I2C
DTS settings with latest DB settings:
- 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO)
- 8040-db: disable cps_i2c0 on CP1
- 8040-db: enable spi1 on CP1 (the new location of the boot flash)
  The spi1 on CP1 is aliased as spi0 since this is the way
  the driver enumerates it.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Masahiro Yamada
6c498835af ARM: uniphier: remove BLK select
This is a user configurable option, but "select BLK" forces users to
enable it.

Even with this commit, BLK is still enabled by "default y if DM_MMC"
for UniPhier SoCs; the difference is users can disable it if they
do not need it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-11 17:55:13 +09:00
Masahiro Yamada
cd62214d98 ARM: dts: uniphier: sync Device Tree with Linux
Sync with the latest kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-11 17:55:01 +09:00
Tom Rini
170397f17d imgtec: Update MAINTAINERS for more config files
Cover all of the boston and malta variations.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-09 15:00:04 -05:00
Jyri Sarha
8c17cbdf8a arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 15:00:03 -05:00
Christian Riesch
177f14da7f calimain: Update maintainers and their email addresses
Signed-off-by: Christian Riesch <christian@riesch.at>
Cc: Manfred Rudigier <manfred.rudigier@omicronenergy.com>
Cc: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
2016-12-09 15:00:02 -05:00
Masahiro Yamada
2411e0fbd9 ARM: uniphier: disable CONFIG_ARCH_FIXUP_FDT_MEMORY
Do not overwrite the memory nodes in the kernel DT where some parts
of the memory region might be carved out.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-10 01:42:51 +09:00
Masahiro Yamada
996fcdadba ARM: uniphier: remove unneeded parentheses
Just a cosmetic cleanup.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-10 01:42:51 +09:00
Masahiro Yamada
82ff6c392f ARM: uniphier: remove unneeded initializer
This will be used to store the return value of readl().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-10 01:42:51 +09:00
Tom Rini
3c643fb01b travis-ci: Switch to building QEMU
First, there are a number of features in newer QEMU that will allow us
to test a wider range of platforms, so we want to use at least v2.8.0.
Second, making use of a PPA for QEMU fails from time to time.  So we
change to checking out and building a copy of QEMU when we know that we
are going to use test.py and need QEMU to be installed.  This adds
around 4 minutes per test.py job that we run.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:23 -05:00
Michal Simek
ebe0f53f48 tools: mkimage: Use fstat instead of stat to avoid malicious hacks
The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e80155)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).

Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c)
where file wasn't checked that it is regular file.

Reported-by: Coverity (CID: 154711, 154712)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:23 -05:00
Fabien Parent
963ed6f323 davinci: omapl138_lcdk: boot from zImage
Stop booting legacy uImage and now boot zImage.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:23 -05:00
Andrew F. Davis
1c9021d622 defconfigs: am57xx_hs_evm: Add default OPTEE load address
Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current AM57xx EVMs.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:22 -05:00
Andrew F. Davis
e3e3c633b6 defconfigs: dra7xx_hs_evm: Add default OPTEE load address
Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current DRA7xx EVMs.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:21 -05:00
Fabien Parent
2b2cab24ac davinci: omapl138_lcdk: fix bad NAND ECC config
The configuration used to error correction was not in line with what
linux and the ROM code is using. Fix it by using the correct
configuration. Now u-boot and the SPL are able to read correctly
anything written by them.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:20 -05:00
Fabien Parent
c0c10449cf davinci: omapl138_lcdk: increase u-boot load size
A size of 0x200 seems way too short for u-boot. Increase the size
to 512k.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:19 -05:00
Yehuda Yitschak
e5f96a872b cmd: pci: add option to parse and display BAR information
Currently the PCI command only allows to see the BAR register
values but not the size and actual base address.
This little extension parses the BAR registers and displays
the base, size and type of each BAR.

Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:18 -05:00
Simon Glass
f831b8e4a4 spl: sandbox: Drop spl_board_announce_boot_device()
This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:18 -05:00
Simon Glass
dd38045dce spl: uniphier: Drop spl_board_announce_boot_device()
This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:17 -05:00
Simon Glass
40ecf52495 spl: sunxi: Drop spl_board_announce_boot_device()
This function is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:16 -05:00
Simon Glass
2acf35dbf7 spl: Drop announce_boot_device()
This task can be handled by inline code now. Drop this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:15 -05:00
Simon Glass
29d357d7bf spl: Pass the loader into spl_load_image()
Rather than have this function figure out the correct loader again, pass
it in as a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:15 -05:00
Simon Glass
540bfe7daa spl: Move the loading code into its own function
Create a boot_from_devices() function to handle trying each device. This
helps to reduce the size of the already-large board_init_r() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:14 -05:00
Simon Glass
ebc4ef61d7 spl: Add a name to the SPL load-image methods
It is useful to name each method so that we can print out this name when
using the method. Currently this happens using a separate function. In
preparation for unifying this, add a name to each method.

The name is only available if we have libcommon support (i.e can use
printf()).

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:13 -05:00
Simon Glass
0d3b059131 spl: Use a single underscore in the SPL_LOAD_IMAGE_METHOD() macro
A double underscore is normally reserved for compiler predefines. Use a
single underscore instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09 08:40:10 -05:00
Keerthy
385d3632ba am57xx: Set tps659038 PMIC GPIO7 pad mux value to POWERHOLD
The GPIO7 pad mux should be programmed to POWERHOLD value
as per board design. In cases where the PMIC is shut off the
mux is set to GPIO7 mode. So during initialization to be on the
safer side set the mode to POWERHOLD.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:40:09 -05:00
Keerthy
97857742f1 configs: omap5_uevm_defconfig: Enable LPAE mode
Enable Linear Physical Address Extension mode which is a
prerequisite for hypervisor mode.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-09 08:39:11 -05:00
Patrick Delaunay
91558c8153 arm: armv7: add us timer for bootstage
solve issue when bootstage is used with armV7 generic timer
first call of timer_get_boot_us() use the function get_timer()
before timer initialization (arch.timer_rate_hz = 0)
=> div by 0

Commit-notes

When I activate bootstage on ARMV7 architecture with platform
using the generic armv7 timer defined in file
./arch/arm/cpu/armv7m/timer.c

I have a issue because gd->arch.timer_rate_hz = 0

For me the get_timer() function should not used before timer_init
(which initialize gd->arch.timer_rate_hz) at least for the ARMV7
timer.

But in the init sequence, the first bootstage fucntion is called
before timer_init and this function use the timer function.

For me it is a error in the generic init sequence :
mark_bootstage is called before timer_init.

static init_fnc_t init_sequence_f[] = {
....
    arch_cpu_init_dm,
    mark_bootstage,        /* need timer, go after init dm */
...
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
        defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
        defined(CONFIG_SPARC)
    timer_init,        /* initialize timer */
#endif
.......

To solve the issue for all the paltform, we can move timer_init()
call just before mark_bootstage() in this array...

It should be ok for ARMV7 but I don't sure for other platform
impacted
- the other ARM platform or ARMV7 wich don't use generic timer
- MIPS BLACKFIN NDS32 or SPARC

and I don't sure of impact for other function called
(board_early_init_f for example....)

=> This patch solve issue only in timer armv7
   get_boot_us() can be called everytime without div by 0 issue
   (gd->arch.timer_rate_hz is not used)

END

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
2016-12-09 08:39:10 -05:00
Tom Rini
361a879902 Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"
This reverts commit 3edc0c2522, reversing
changes made to bb135a0180.
2016-12-09 07:56:54 -05:00
Tom Rini
3edc0c2522 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-12-09 07:10:39 -05:00
Alex
bb135a0180 net/phy/vitesse: Rework RGMII skew configuration for VSC8601
The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.

Tested on custom board with AM3352 SOC and VSC801 PHY.

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:22 -06:00
Stefan Roese
c7ac15388e net: usb: r8152: Use ALLOC_CACHE_ALIGN_BUFFER() to allocate the buffers
Testing on theadorable (Armada XP) has shown, that using this driver
results in many cache misaligned warning, such as:

CACHE: Misaligned operation at range [7fabd8fc, 7fabd900]

This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the
buffers on a cache aligned boundary. This fixes all warnings seen on the
Armada XP platform.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ted Chen <tedchen@realtek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:22 -06:00
shaohui xie
bead08800a net: fman: fix 2.5G SGMII settings
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:22 -06:00
oliver@schinagl.nl
cebf3f558e net: phy: realtek: Only force master mode on rtl8211b/c
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.

The bug that define tried to solve was a buggy PLL in the RTL8211C only.

The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:22 -06:00
oliver@schinagl.nl
cbe40e116d net: phy: realtek: make define more consistent
All internal defines in the realtek phy are with a small X,
except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:22 -06:00
oliver@schinagl.nl
020f67628d net: phy: realtek: Use the BIT() macro
The BIT macro is the preferred method to set bits.
This patch adds the bit macro and converts bit invocations.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:21 -06:00
Marek Vasut
75c056d70e net: phy: micrel: Fix error handling
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.

drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
  for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
  ^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
   if (ret)
   ^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
  for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
  ^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
   if (ret)
   ^~

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-08 10:36:21 -06:00
Michal Simek
b63cb3abbc net: xilinx: Use mdio_register_seq() to support multiple instances
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.

Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
2016-12-08 10:34:42 +01:00